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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm64/include/asm/pgtable-hwdef.h
....@@ -1,17 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2012 ARM Ltd.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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- *
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- * You should have received a copy of the GNU General Public License
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- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 #ifndef __ASM_PGTABLE_HWDEF_H
176 #define __ASM_PGTABLE_HWDEF_H
....@@ -40,7 +29,7 @@
4029  * Size mapped by an entry at level n ( 0 <= n <= 3)
4130  * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits
4231  * in the final page. The maximum number of translation levels supported by
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- * the architecture is 4. Hence, starting at at level n, we have further
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+ * the architecture is 4. Hence, starting at level n, we have further
4433  * ((4 - n) - 1) levels of translation excluding the offset within the page.
4534  * So, the total number of bits mapped by an entry at level n is :
4635  *
....@@ -92,25 +81,15 @@
9281 /*
9382  * Contiguous page definitions.
9483  */
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-#ifdef CONFIG_ARM64_64K_PAGES
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-#define CONT_PTE_SHIFT		5
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-#define CONT_PMD_SHIFT		5
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-#elif defined(CONFIG_ARM64_16K_PAGES)
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-#define CONT_PTE_SHIFT		7
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-#define CONT_PMD_SHIFT		5
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-#else
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-#define CONT_PTE_SHIFT		4
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-#define CONT_PMD_SHIFT		4
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-#endif
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-
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-#define CONT_PTES		(1 << CONT_PTE_SHIFT)
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+#define CONT_PTE_SHIFT		(CONFIG_ARM64_CONT_PTE_SHIFT + PAGE_SHIFT)
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+#define CONT_PTES		(1 << (CONT_PTE_SHIFT - PAGE_SHIFT))
10786 #define CONT_PTE_SIZE		(CONT_PTES * PAGE_SIZE)
10887 #define CONT_PTE_MASK		(~(CONT_PTE_SIZE - 1))
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-#define CONT_PMDS		(1 << CONT_PMD_SHIFT)
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+
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+#define CONT_PMD_SHIFT		(CONFIG_ARM64_CONT_PMD_SHIFT + PMD_SHIFT)
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+#define CONT_PMDS		(1 << (CONT_PMD_SHIFT - PMD_SHIFT))
11091 #define CONT_PMD_SIZE		(CONT_PMDS * PMD_SIZE)
11192 #define CONT_PMD_MASK		(~(CONT_PMD_SIZE - 1))
112
-/* the the numerical offset of the PTE within a range of CONT_PTES */
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-#define CONT_RANGE_OFFSET(addr) (((addr)>>PAGE_SHIFT)&(CONT_PTES-1))
11493 
11594 /*
11695  * Hardware page table definitions.
....@@ -121,12 +100,12 @@
121100 #define PUD_TABLE_BIT		(_AT(pudval_t, 1) << 1)
122101 #define PUD_TYPE_MASK		(_AT(pudval_t, 3) << 0)
123102 #define PUD_TYPE_SECT		(_AT(pudval_t, 1) << 0)
103
+#define PUD_SECT_RDONLY		(_AT(pudval_t, 1) << 7)		/* AP[2] */
124104 
125105 /*
126106  * Level 2 descriptor (PMD).
127107  */
128108 #define PMD_TYPE_MASK		(_AT(pmdval_t, 3) << 0)
129
-#define PMD_TYPE_FAULT		(_AT(pmdval_t, 0) << 0)
130109 #define PMD_TYPE_TABLE		(_AT(pmdval_t, 3) << 0)
131110 #define PMD_TYPE_SECT		(_AT(pmdval_t, 1) << 0)
132111 #define PMD_TABLE_BIT		(_AT(pmdval_t, 1) << 1)
....@@ -153,8 +132,8 @@
153132 /*
154133  * Level 3 descriptor (PTE).
155134  */
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+#define PTE_VALID		(_AT(pteval_t, 1) << 0)
156136 #define PTE_TYPE_MASK		(_AT(pteval_t, 3) << 0)
157
-#define PTE_TYPE_FAULT		(_AT(pteval_t, 0) << 0)
158137 #define PTE_TYPE_PAGE		(_AT(pteval_t, 3) << 0)
159138 #define PTE_TABLE_BIT		(_AT(pteval_t, 1) << 1)
160139 #define PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
....@@ -162,11 +141,11 @@
162141 #define PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
163142 #define PTE_AF			(_AT(pteval_t, 1) << 10)	/* Access Flag */
164143 #define PTE_NG			(_AT(pteval_t, 1) << 11)	/* nG */
144
+#define PTE_GP			(_AT(pteval_t, 1) << 50)	/* BTI guarded */
165145 #define PTE_DBM			(_AT(pteval_t, 1) << 51)	/* Dirty Bit Management */
166146 #define PTE_CONT		(_AT(pteval_t, 1) << 52)	/* Contiguous range */
167147 #define PTE_PXN			(_AT(pteval_t, 1) << 53)	/* Privileged XN */
168148 #define PTE_UXN			(_AT(pteval_t, 1) << 54)	/* User XN */
169
-#define PTE_HYP_XN		(_AT(pteval_t, 1) << 54)	/* HYP XN */
170149 
171150 #define PTE_ADDR_LOW		(((_AT(pteval_t, 1) << (48 - PAGE_SHIFT)) - 1) << PAGE_SHIFT)
172151 #ifdef CONFIG_ARM64_PA_BITS_52
....@@ -183,33 +162,17 @@
183162 #define PTE_ATTRINDX_MASK	(_AT(pteval_t, 7) << 2)
184163 
185164 /*
186
- * 2nd stage PTE definitions
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- */
188
-#define PTE_S2_RDONLY		(_AT(pteval_t, 1) << 6)   /* HAP[2:1] */
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-#define PTE_S2_RDWR		(_AT(pteval_t, 3) << 6)   /* HAP[2:1] */
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-#define PTE_S2_XN		(_AT(pteval_t, 2) << 53)  /* XN[1:0] */
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-
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-#define PMD_S2_RDONLY		(_AT(pmdval_t, 1) << 6)   /* HAP[2:1] */
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-#define PMD_S2_RDWR		(_AT(pmdval_t, 3) << 6)   /* HAP[2:1] */
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-#define PMD_S2_XN		(_AT(pmdval_t, 2) << 53)  /* XN[1:0] */
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-
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-/*
197165  * Memory Attribute override for Stage-2 (MemAttr[3:0])
198166  */
199167 #define PTE_S2_MEMATTR(t)	(_AT(pteval_t, (t)) << 2)
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-#define PTE_S2_MEMATTR_MASK	(_AT(pteval_t, 0xf) << 2)
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-
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-/*
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- * EL2/HYP PTE/PMD definitions
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- */
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-#define PMD_HYP			PMD_SECT_USER
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-#define PTE_HYP			PTE_USER
207168 
208169 /*
209170  * Highest possible physical address supported.
210171  */
211172 #define PHYS_MASK_SHIFT		(CONFIG_ARM64_PA_BITS)
212173 #define PHYS_MASK		((UL(1) << PHYS_MASK_SHIFT) - 1)
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+
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+#define TTBR_CNP_BIT		(UL(1) << 0)
213176 
214177 /*
215178  * TCR flags.
....@@ -221,7 +184,10 @@
221184 #define TCR_TxSZ(x)		(TCR_T0SZ(x) | TCR_T1SZ(x))
222185 #define TCR_TxSZ_WIDTH		6
223186 #define TCR_T0SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T0SZ_OFFSET)
187
+#define TCR_T1SZ_MASK		(((UL(1) << TCR_TxSZ_WIDTH) - 1) << TCR_T1SZ_OFFSET)
224188 
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+#define TCR_EPD0_SHIFT		7
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+#define TCR_EPD0_MASK		(UL(1) << TCR_EPD0_SHIFT)
225191 #define TCR_IRGN0_SHIFT		8
226192 #define TCR_IRGN0_MASK		(UL(3) << TCR_IRGN0_SHIFT)
227193 #define TCR_IRGN0_NC		(UL(0) << TCR_IRGN0_SHIFT)
....@@ -229,6 +195,8 @@
229195 #define TCR_IRGN0_WT		(UL(2) << TCR_IRGN0_SHIFT)
230196 #define TCR_IRGN0_WBnWA		(UL(3) << TCR_IRGN0_SHIFT)
231197 
198
+#define TCR_EPD1_SHIFT		23
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+#define TCR_EPD1_MASK		(UL(1) << TCR_EPD1_SHIFT)
232200 #define TCR_IRGN1_SHIFT		24
233201 #define TCR_IRGN1_MASK		(UL(3) << TCR_IRGN1_SHIFT)
234202 #define TCR_IRGN1_NC		(UL(0) << TCR_IRGN1_SHIFT)
....@@ -292,7 +260,11 @@
292260 #define TCR_TBI1		(UL(1) << 38)
293261 #define TCR_HA			(UL(1) << 39)
294262 #define TCR_HD			(UL(1) << 40)
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+#define TCR_TBID1		(UL(1) << 52)
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+#define TCR_NFD0		(UL(1) << 53)
295265 #define TCR_NFD1		(UL(1) << 54)
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+#define TCR_E0PD0		(UL(1) << 55)
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+#define TCR_E0PD1		(UL(1) << 56)
296268 
297269 /*
298270  * TTBR.
....@@ -305,4 +277,10 @@
305277 #define TTBR_BADDR_MASK_52	(((UL(1) << 46) - 1) << 2)
306278 #endif
307279 
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+#ifdef CONFIG_ARM64_VA_BITS_52
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+/* Must be at least 64-byte aligned to prevent corruption of the TTBR */
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+#define TTBR1_BADDR_4852_OFFSET	(((UL(1) << (52 - PGDIR_SHIFT)) - \
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+				 (UL(1) << (48 - PGDIR_SHIFT))) * 8)
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+#endif
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+
308286 #endif