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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/mach-tegra/sleep-tegra30.S
....@@ -1,17 +1,6 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify it
5
- * under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11
- * more details.
12
- *
13
- * You should have received a copy of the GNU General Public License
14
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 
176 #include <linux/linkage.h>
....@@ -29,7 +18,6 @@
2918 #define EMC_CFG				0xc
3019 #define EMC_ADR_CFG			0x10
3120 #define EMC_TIMING_CONTROL		0x28
32
-#define EMC_REFRESH			0x70
3321 #define EMC_NOP				0xdc
3422 #define EMC_SELF_REF			0xe0
3523 #define EMC_MRW				0xe8
....@@ -71,6 +59,9 @@
7159 #define CLK_RESET_PLLX_MISC3_IDDQ	3
7260 #define CLK_RESET_PLLM_MISC_IDDQ	5
7361 #define CLK_RESET_PLLC_MISC_IDDQ	26
62
+#define CLK_RESET_PLLP_RESHIFT		0x528
63
+#define CLK_RESET_PLLP_RESHIFT_DEFAULT	0x3b
64
+#define CLK_RESET_PLLP_RESHIFT_ENABLE	0x3
7465 
7566 #define CLK_RESET_CLK_SOURCE_MSELECT	0x3b4
7667 
....@@ -274,11 +265,11 @@
274265 ENDPROC(tegra30_sleep_core_finish)
275266 
276267 /*
277
- * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
268
+ * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg)
278269  *
279270  * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
280271  */
281
-ENTRY(tegra30_sleep_cpu_secondary_finish)
272
+ENTRY(tegra30_pm_secondary_cpu_suspend)
282273 	mov	r7, lr
283274 
284275 	/* Flush and disable the L1 data cache */
....@@ -290,7 +281,7 @@
290281 	bl	tegra30_cpu_shutdown
291282 	mov	r0, #1                          @ never return here
292283 	ret	r7
293
-ENDPROC(tegra30_sleep_cpu_secondary_finish)
284
+ENDPROC(tegra30_pm_secondary_cpu_suspend)
294285 
295286 /*
296287  * tegra30_tear_down_cpu
....@@ -370,7 +361,6 @@
370361 
371362 	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
372363 	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
373
-	pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
374364 
375365 _pll_m_c_x_done:
376366 	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
....@@ -380,14 +370,24 @@
380370 	pll_locked r1, r0, CLK_RESET_PLLP_BASE
381371 	pll_locked r1, r0, CLK_RESET_PLLA_BASE
382372 	pll_locked r1, r0, CLK_RESET_PLLC_BASE
383
-	pll_locked r1, r0, CLK_RESET_PLLX_BASE
384373 
374
+	/*
375
+	 * CPUFreq driver could select other PLL for CPU. PLLX will be
376
+	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
377
+	 * tegra30_cpu_clock_resume().
378
+	 */
385379 	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
386380 	cmp	r1, #TEGRA30
387381 	beq	1f
382
+
383
+	pll_locked r1, r0, CLK_RESET_PLLX_BASE
384
+
388385 	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]
389386 	bic	r1, r1, #(1<<31)	@ disable PllP bypass
390387 	str	r1, [r0, #CLK_RESET_PLLP_BASE]
388
+
389
+	mov	r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
390
+	str	r1, [r0, #CLK_RESET_PLLP_RESHIFT]
391391 1:
392392 
393393 	mov32	r7, TEGRA_TMRUS_BASE
....@@ -403,11 +403,8 @@
403403 	ldr	r4, [r5, #0x1C]		@ restore SCLK_BURST
404404 	str	r4, [r0, #CLK_RESET_SCLK_BURST]
405405 
406
-	cmp	r10, #TEGRA30
407
-	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX
408
-	movteq	r4, #:upper16:((1 << 28) | (0x8))
409
-	movwne	r4, #:lower16:((1 << 28) | (0xe))
410
-	movtne	r4, #:upper16:((1 << 28) | (0xe))
406
+	movw	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP
407
+	movt	r4, #:upper16:((1 << 28) | (0x4))
411408 	str	r4, [r0, #CLK_RESET_CCLK_BURST]
412409 
413410 	/* Restore pad power state to normal */
....@@ -467,7 +464,6 @@
467464 	cmp	r10, #TEGRA30
468465 	streq	r1, [r0, #EMC_NOP]
469466 	streq	r1, [r0, #EMC_NOP]
470
-	streq	r1, [r0, #EMC_REFRESH]
471467 
472468 	emc_device_mask r1, r0
473469 
....@@ -528,6 +524,8 @@
528524 	str	r1, [r0, #EMC_ZCAL_INTERVAL]
529525 	ldr	r1, [r5, #0x0]		@ restore EMC_CFG
530526 	str	r1, [r0, #EMC_CFG]
527
+
528
+	emc_timing_update r1, r0
531529 
532530 	/* Tegra114 had dual EMC channel, now config the other one */
533531 	cmp	r10, #TEGRA114
....@@ -655,6 +653,10 @@
655653 	orrne	r0, r0, #(1 << 31)	@ enable PllP bypass on fast cluster
656654 	bic	r0, r0, #(1 << 30)
657655 	str	r0, [r5, #CLK_RESET_PLLP_BASE]
656
+	beq	1f
657
+	mov	r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
658
+	str	r0, [r5, #CLK_RESET_PLLP_RESHIFT]
659
+1:
658660 	ldr	r0, [r5, #CLK_RESET_PLLA_BASE]
659661 	bic	r0, r0, #(1 << 30)
660662 	str	r0, [r5, #CLK_RESET_PLLA_BASE]
....@@ -670,8 +672,12 @@
670672 	pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
671673 _no_pll_in_iddq:
672674 
673
-	/* switch to CLKS */
674
-	mov	r0, #0	/* brust policy = 32KHz */
675
+	/*
676
+	 * Switch to clk_s (32KHz); bits 28:31=0
677
+	 * Enable burst on CPU IRQ; bit 24=1
678
+	 * Set IRQ burst clock source to clk_m; bits 10:8=0
679
+	 */
680
+	mov	r0, #(1 << 24)
675681 	str	r0, [r5, #CLK_RESET_SCLK_BURST]
676682 
677683 	ret	lr
....@@ -704,10 +710,12 @@
704710 	dsb
705711 	ldr	r0, [r6, r2] /* memory barrier */
706712 
713
+	cmp	r10, #TEGRA30
707714 halted:
708715 	isb
709716 	dsb
710
-	wfi	/* CPU should be power gated here */
717
+	wfine	/* CPU should be power gated here */
718
+	wfeeq
711719 
712720 	/* !!!FIXME!!! Implement halt failure handler */
713721 	b	halted