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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/mach-davinci/devices-da8xx.c
....@@ -1,22 +1,19 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * DA8XX/OMAP L1XX platform device data
34  *
45  * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
56  * Derived from code that was:
67  *	Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
128  */
139 #include <linux/ahci_platform.h>
1410 #include <linux/clk-provider.h>
1511 #include <linux/clk.h>
1612 #include <linux/clkdev.h>
17
-#include <linux/dma-contiguous.h>
13
+#include <linux/dma-map-ops.h>
1814 #include <linux/dmaengine.h>
1915 #include <linux/init.h>
16
+#include <linux/io.h>
2017 #include <linux/platform_device.h>
2118 #include <linux/reboot.h>
2219 #include <linux/serial_8250.h>
....@@ -24,10 +21,10 @@
2421 #include <mach/common.h>
2522 #include <mach/cputype.h>
2623 #include <mach/da8xx.h>
27
-#include <mach/time.h>
2824 
2925 #include "asp.h"
3026 #include "cpuidle.h"
27
+#include "irqs.h"
3128 #include "sram.h"
3229 
3330 #define DA8XX_TPCC_BASE			0x01c00000
....@@ -64,7 +61,7 @@
6461 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
6562 	{
6663 		.mapbase	= DA8XX_UART0_BASE,
67
-		.irq		= IRQ_DA8XX_UARTINT0,
64
+		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
6865 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
6966 					UPF_IOREMAP,
7067 		.iotype		= UPIO_MEM,
....@@ -77,7 +74,7 @@
7774 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
7875 	{
7976 		.mapbase	= DA8XX_UART1_BASE,
80
-		.irq		= IRQ_DA8XX_UARTINT1,
77
+		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
8178 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
8279 					UPF_IOREMAP,
8380 		.iotype		= UPIO_MEM,
....@@ -90,7 +87,7 @@
9087 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
9188 	{
9289 		.mapbase	= DA8XX_UART2_BASE,
93
-		.irq		= IRQ_DA8XX_UARTINT2,
90
+		.irq		= DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
9491 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
9592 					UPF_IOREMAP,
9693 		.iotype		= UPIO_MEM,
....@@ -171,12 +168,12 @@
171168 	},
172169 	{
173170 		.name	= "edma3_ccint",
174
-		.start	= IRQ_DA8XX_CCINT0,
171
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
175172 		.flags	= IORESOURCE_IRQ,
176173 	},
177174 	{
178175 		.name	= "edma3_ccerrint",
179
-		.start	= IRQ_DA8XX_CCERRINT,
176
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
180177 		.flags	= IORESOURCE_IRQ,
181178 	},
182179 };
....@@ -196,12 +193,12 @@
196193 	},
197194 	{
198195 		.name	= "edma3_ccint",
199
-		.start	= IRQ_DA850_CCINT1,
196
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
200197 		.flags	= IORESOURCE_IRQ,
201198 	},
202199 	{
203200 		.name	= "edma3_ccerrint",
204
-		.start	= IRQ_DA850_CCERRINT1,
201
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
205202 		.flags	= IORESOURCE_IRQ,
206203 	},
207204 };
....@@ -306,8 +303,8 @@
306303 		.flags	= IORESOURCE_MEM,
307304 	},
308305 	{
309
-		.start	= IRQ_DA8XX_I2CINT0,
310
-		.end	= IRQ_DA8XX_I2CINT0,
306
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
307
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
311308 		.flags	= IORESOURCE_IRQ,
312309 	},
313310 };
....@@ -326,8 +323,8 @@
326323 		.flags	= IORESOURCE_MEM,
327324 	},
328325 	{
329
-		.start	= IRQ_DA8XX_I2CINT1,
330
-		.end	= IRQ_DA8XX_I2CINT1,
326
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
327
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
331328 		.flags	= IORESOURCE_IRQ,
332329 	},
333330 };
....@@ -382,23 +379,23 @@
382379 		.flags	= IORESOURCE_MEM,
383380 	},
384381 	{
385
-		.start	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
386
-		.end	= IRQ_DA8XX_C0_RX_THRESH_PULSE,
382
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
383
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
387384 		.flags	= IORESOURCE_IRQ,
388385 	},
389386 	{
390
-		.start	= IRQ_DA8XX_C0_RX_PULSE,
391
-		.end	= IRQ_DA8XX_C0_RX_PULSE,
387
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
388
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
392389 		.flags	= IORESOURCE_IRQ,
393390 	},
394391 	{
395
-		.start	= IRQ_DA8XX_C0_TX_PULSE,
396
-		.end	= IRQ_DA8XX_C0_TX_PULSE,
392
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
393
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
397394 		.flags	= IORESOURCE_IRQ,
398395 	},
399396 	{
400
-		.start	= IRQ_DA8XX_C0_MISC_PULSE,
401
-		.end	= IRQ_DA8XX_C0_MISC_PULSE,
397
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
398
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
402399 		.flags	= IORESOURCE_IRQ,
403400 	},
404401 };
....@@ -470,7 +467,7 @@
470467 	},
471468 	{
472469 		.name	= "common",
473
-		.start	= IRQ_DA8XX_MCASPINT,
470
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
474471 		.flags	= IORESOURCE_IRQ,
475472 	},
476473 };
....@@ -505,7 +502,7 @@
505502 	},
506503 	{
507504 		.name	= "common",
508
-		.start	= IRQ_DA8XX_MCASPINT,
505
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
509506 		.flags	= IORESOURCE_IRQ,
510507 	},
511508 };
....@@ -540,7 +537,7 @@
540537 	},
541538 	{
542539 		.name	= "common",
543
-		.start	= IRQ_DA8XX_MCASPINT,
540
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
544541 		.flags	= IORESOURCE_IRQ,
545542 	},
546543 };
....@@ -588,43 +585,43 @@
588585 		.flags	= IORESOURCE_MEM,
589586 	},
590587 	{
591
-		.start	= IRQ_DA8XX_EVTOUT0,
592
-		.end	= IRQ_DA8XX_EVTOUT0,
588
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
589
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
593590 		.flags	= IORESOURCE_IRQ,
594591 	},
595592 	{
596
-		.start	= IRQ_DA8XX_EVTOUT1,
597
-		.end	= IRQ_DA8XX_EVTOUT1,
593
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
594
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
598595 		.flags	= IORESOURCE_IRQ,
599596 	},
600597 	{
601
-		.start	= IRQ_DA8XX_EVTOUT2,
602
-		.end	= IRQ_DA8XX_EVTOUT2,
598
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
599
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
603600 		.flags	= IORESOURCE_IRQ,
604601 	},
605602 	{
606
-		.start	= IRQ_DA8XX_EVTOUT3,
607
-		.end	= IRQ_DA8XX_EVTOUT3,
603
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
604
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
608605 		.flags	= IORESOURCE_IRQ,
609606 	},
610607 	{
611
-		.start	= IRQ_DA8XX_EVTOUT4,
612
-		.end	= IRQ_DA8XX_EVTOUT4,
608
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
609
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
613610 		.flags	= IORESOURCE_IRQ,
614611 	},
615612 	{
616
-		.start	= IRQ_DA8XX_EVTOUT5,
617
-		.end	= IRQ_DA8XX_EVTOUT5,
613
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
614
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
618615 		.flags	= IORESOURCE_IRQ,
619616 	},
620617 	{
621
-		.start	= IRQ_DA8XX_EVTOUT6,
622
-		.end	= IRQ_DA8XX_EVTOUT6,
618
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
619
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
623620 		.flags	= IORESOURCE_IRQ,
624621 	},
625622 	{
626
-		.start	= IRQ_DA8XX_EVTOUT7,
627
-		.end	= IRQ_DA8XX_EVTOUT7,
623
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
624
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
628625 		.flags	= IORESOURCE_IRQ,
629626 	},
630627 };
....@@ -674,8 +671,8 @@
674671 		.flags  = IORESOURCE_MEM,
675672 	},
676673 	[1] = { /* interrupt */
677
-		.start  = IRQ_DA8XX_LCDINT,
678
-		.end    = IRQ_DA8XX_LCDINT,
674
+		.start  = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
675
+		.end    = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
679676 		.flags  = IORESOURCE_IRQ,
680677 	},
681678 };
....@@ -703,48 +700,48 @@
703700 		.flags	= IORESOURCE_MEM,
704701 	},
705702 	{ /* interrupt */
706
-		.start	= IRQ_DA8XX_GPIO0,
707
-		.end	= IRQ_DA8XX_GPIO0,
703
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
704
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
708705 		.flags	= IORESOURCE_IRQ,
709706 	},
710707 	{
711
-		.start	= IRQ_DA8XX_GPIO1,
712
-		.end	= IRQ_DA8XX_GPIO1,
708
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
709
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
713710 		.flags	= IORESOURCE_IRQ,
714711 	},
715712 	{
716
-		.start	= IRQ_DA8XX_GPIO2,
717
-		.end	= IRQ_DA8XX_GPIO2,
713
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
714
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
718715 		.flags	= IORESOURCE_IRQ,
719716 	},
720717 	{
721
-		.start	= IRQ_DA8XX_GPIO3,
722
-		.end	= IRQ_DA8XX_GPIO3,
718
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
719
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
723720 		.flags	= IORESOURCE_IRQ,
724721 	},
725722 	{
726
-		.start	= IRQ_DA8XX_GPIO4,
727
-		.end	= IRQ_DA8XX_GPIO4,
723
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
724
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
728725 		.flags	= IORESOURCE_IRQ,
729726 	},
730727 	{
731
-		.start	= IRQ_DA8XX_GPIO5,
732
-		.end	= IRQ_DA8XX_GPIO5,
728
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
729
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
733730 		.flags	= IORESOURCE_IRQ,
734731 	},
735732 	{
736
-		.start	= IRQ_DA8XX_GPIO6,
737
-		.end	= IRQ_DA8XX_GPIO6,
733
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
734
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
738735 		.flags	= IORESOURCE_IRQ,
739736 	},
740737 	{
741
-		.start	= IRQ_DA8XX_GPIO7,
742
-		.end	= IRQ_DA8XX_GPIO7,
738
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
739
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
743740 		.flags	= IORESOURCE_IRQ,
744741 	},
745742 	{
746
-		.start	= IRQ_DA8XX_GPIO8,
747
-		.end	= IRQ_DA8XX_GPIO8,
743
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
744
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
748745 		.flags	= IORESOURCE_IRQ,
749746 	},
750747 };
....@@ -769,8 +766,8 @@
769766 		.flags	= IORESOURCE_MEM,
770767 	},
771768 	{		/* interrupt */
772
-		.start	= IRQ_DA8XX_MMCSDINT0,
773
-		.end	= IRQ_DA8XX_MMCSDINT0,
769
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
770
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
774771 		.flags	= IORESOURCE_IRQ,
775772 	},
776773 };
....@@ -796,8 +793,8 @@
796793 		.flags	= IORESOURCE_MEM,
797794 	},
798795 	{		/* interrupt */
799
-		.start	= IRQ_DA850_MMCSDINT0_1,
800
-		.end	= IRQ_DA850_MMCSDINT0_1,
796
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
797
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
801798 		.flags	= IORESOURCE_IRQ,
802799 	},
803800 };
....@@ -848,8 +845,8 @@
848845 		.flags		= IORESOURCE_MEM,
849846 	},
850847 	{ /* dsp irq */
851
-		.start		= IRQ_DA8XX_CHIPINT0,
852
-		.end		= IRQ_DA8XX_CHIPINT0,
848
+		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
849
+		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
853850 		.flags		= IORESOURCE_IRQ,
854851 	},
855852 };
....@@ -887,6 +884,7 @@
887884 
888885 void __init da8xx_rproc_reserve_cma(void)
889886 {
887
+	struct cma *cma;
890888 	int ret;
891889 
892890 	if (!rproc_base || !rproc_size) {
....@@ -900,13 +898,16 @@
900898 	pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
901899 		__func__, rproc_size, (unsigned long)rproc_base);
902900 
903
-	ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
904
-	if (ret)
905
-		pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
906
-	else
907
-		rproc_mem_inited = true;
901
+	ret = dma_contiguous_reserve_area(rproc_size, rproc_base, 0, &cma,
902
+			true);
903
+	if (ret) {
904
+		pr_err("%s: dma_contiguous_reserve_area failed %d\n",
905
+			__func__, ret);
906
+		return;
907
+	}
908
+	da8xx_dsp.dev.cma_area = cma;
909
+	rproc_mem_inited = true;
908910 }
909
-
910911 #else
911912 
912913 void __init da8xx_rproc_reserve_cma(void)
....@@ -939,13 +940,13 @@
939940 		.flags		= IORESOURCE_MEM,
940941 	},
941942 	{ /* timer irq */
942
-		.start		= IRQ_DA8XX_RTC,
943
-		.end		= IRQ_DA8XX_RTC,
943
+		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
944
+		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
944945 		.flags		= IORESOURCE_IRQ,
945946 	},
946947 	{ /* alarm irq */
947
-		.start		= IRQ_DA8XX_RTC,
948
-		.end		= IRQ_DA8XX_RTC,
948
+		.start		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
949
+		.end		= DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
949950 		.flags		= IORESOURCE_IRQ,
950951 	},
951952 };
....@@ -1012,8 +1013,8 @@
10121013 		.flags	= IORESOURCE_MEM,
10131014 	},
10141015 	[1] = {
1015
-		.start	= IRQ_DA8XX_SPINT0,
1016
-		.end	= IRQ_DA8XX_SPINT0,
1016
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1017
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
10171018 		.flags	= IORESOURCE_IRQ,
10181019 	},
10191020 };
....@@ -1025,8 +1026,8 @@
10251026 		.flags	= IORESOURCE_MEM,
10261027 	},
10271028 	[1] = {
1028
-		.start	= IRQ_DA8XX_SPINT1,
1029
-		.end	= IRQ_DA8XX_SPINT1,
1029
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1030
+		.end	= DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
10301031 		.flags	= IORESOURCE_IRQ,
10311032 	},
10321033 };
....@@ -1106,7 +1107,7 @@
11061107 		.flags	= IORESOURCE_MEM,
11071108 	},
11081109 	{
1109
-		.start	= IRQ_DA850_SATAINT,
1110
+		.start	= DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
11101111 		.flags	= IORESOURCE_IRQ,
11111112 	},
11121113 };