add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/crypto/ghash-ce-core.S
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@@ -1,15 +1,15 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Accelerated GHASH implementation with NEON/ARMv8 vmull.p8/64 instructions.
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  *
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  * Copyright (C) 2015 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org>
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms of the GNU General Public License version 2 as published
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- * by the Free Software Foundation.
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  */
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 #include <linux/linkage.h>
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 #include <asm/assembler.h>
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+
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+	.arch		armv8-a
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+	.fpu		crypto-neon-fp-armv8
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 	SHASH		.req	q0
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 	T1		.req	q1
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@@ -63,8 +63,34 @@
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 	k48		.req	d31
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 	SHASH2_p64	.req	d31
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+	HH		.req	q10
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+	HH3		.req	q11
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+	HH4		.req	q12
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+	HH34		.req	q13
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+
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+	HH_L		.req	d20
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+	HH_H		.req	d21
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+	HH3_L		.req	d22
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+	HH3_H		.req	d23
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+	HH4_L		.req	d24
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+	HH4_H		.req	d25
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+	HH34_L		.req	d26
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+	HH34_H		.req	d27
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+	SHASH2_H	.req	d29
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+
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+	XL2		.req	q5
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+	XM2		.req	q6
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+	XH2		.req	q7
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+	T3		.req	q8
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+
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+	XL2_L		.req	d10
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+	XL2_H		.req	d11
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+	XM2_L		.req	d12
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+	XM2_H		.req	d13
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+	T3_L		.req	d16
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+	T3_H		.req	d17
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+
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 	.text
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-	.fpu		crypto-neon-fp-armv8
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 	.macro		__pmull_p64, rd, rn, rm, b1, b2, b3, b4
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 	vmull.p64	\rd, \rn, \rm
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@@ -175,12 +201,77 @@
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 	beq		0f
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 	vld1.64		{T1}, [ip]
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 	teq		r0, #0
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-	b		1f
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+	b		3f
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-0:	vld1.64		{T1}, [r2]!
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+0:	.ifc		\pn, p64
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+	tst		r0, #3			// skip until #blocks is a
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+	bne		2f			// round multiple of 4
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+
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+	vld1.8		{XL2-XM2}, [r2]!
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+1:	vld1.8		{T3-T2}, [r2]!
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+	vrev64.8	XL2, XL2
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+	vrev64.8	XM2, XM2
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+
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+	subs		r0, r0, #4
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+
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+	vext.8		T1, XL2, XL2, #8
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+	veor		XL2_H, XL2_H, XL_L
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+	veor		XL, XL, T1
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+
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+	vrev64.8	T3, T3
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+	vrev64.8	T1, T2
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+
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+	vmull.p64	XH, HH4_H, XL_H			// a1 * b1
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+	veor		XL2_H, XL2_H, XL_H
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+	vmull.p64	XL, HH4_L, XL_L			// a0 * b0
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+	vmull.p64	XM, HH34_H, XL2_H		// (a1 + a0)(b1 + b0)
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+
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+	vmull.p64	XH2, HH3_H, XM2_L		// a1 * b1
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+	veor		XM2_L, XM2_L, XM2_H
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+	vmull.p64	XL2, HH3_L, XM2_H		// a0 * b0
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+	vmull.p64	XM2, HH34_L, XM2_L		// (a1 + a0)(b1 + b0)
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+
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+	veor		XH, XH, XH2
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+	veor		XL, XL, XL2
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+	veor		XM, XM, XM2
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+
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+	vmull.p64	XH2, HH_H, T3_L			// a1 * b1
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+	veor		T3_L, T3_L, T3_H
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+	vmull.p64	XL2, HH_L, T3_H			// a0 * b0
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+	vmull.p64	XM2, SHASH2_H, T3_L		// (a1 + a0)(b1 + b0)
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+
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+	veor		XH, XH, XH2
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+	veor		XL, XL, XL2
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+	veor		XM, XM, XM2
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+
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+	vmull.p64	XH2, SHASH_H, T1_L		// a1 * b1
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+	veor		T1_L, T1_L, T1_H
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+	vmull.p64	XL2, SHASH_L, T1_H		// a0 * b0
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+	vmull.p64	XM2, SHASH2_p64, T1_L		// (a1 + a0)(b1 + b0)
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+
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+	veor		XH, XH, XH2
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+	veor		XL, XL, XL2
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+	veor		XM, XM, XM2
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+
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+	beq		4f
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+
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+	vld1.8		{XL2-XM2}, [r2]!
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+
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+	veor		T1, XL, XH
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+	veor		XM, XM, T1
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+
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+	__pmull_reduce_p64
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+
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+	veor		T1, T1, XH
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+	veor		XL, XL, T1
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+
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+	b		1b
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+	.endif
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+
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+2:	vld1.64		{T1}, [r2]!
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 	subs		r0, r0, #1
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-1:	/* multiply XL by SHASH in GF(2^128) */
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+3:	/* multiply XL by SHASH in GF(2^128) */
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 #ifndef CONFIG_CPU_BIG_ENDIAN
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 	vrev64.8	T1, T1
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 #endif
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@@ -193,7 +284,7 @@
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 	__pmull_\pn	XL, XL_L, SHASH_L, s1l, s2l, s3l, s4l	@ a0 * b0
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 	__pmull_\pn	XM, T1_L, SHASH2_\pn			@ (a1+a0)(b1+b0)
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-	veor		T1, XL, XH
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+4:	veor		T1, XL, XH
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 	veor		XM, XM, T1
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 	__pmull_reduce_\pn
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@@ -212,8 +303,14 @@
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 	 *			   struct ghash_key const *k, const char *head)
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 	 */
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 ENTRY(pmull_ghash_update_p64)
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-	vld1.64		{SHASH}, [r3]
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+	vld1.64		{SHASH}, [r3]!
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+	vld1.64		{HH}, [r3]!
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+	vld1.64		{HH3-HH4}, [r3]
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+
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 	veor		SHASH2_p64, SHASH_L, SHASH_H
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+	veor		SHASH2_H, HH_L, HH_H
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+	veor		HH34_L, HH3_L, HH3_H
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+	veor		HH34_H, HH4_L, HH4_H
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 	vmov.i8		MASK, #0xe1
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 	vshl.u64	MASK, MASK, #57