add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/zynq-7000.dtsi
..
..
@@ -59,6 +59,39 @@
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 		regulator-always-on;
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 	};
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+	replicator {
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+		compatible = "arm,coresight-static-replicator";
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+		clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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+		clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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+
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+		out-ports {
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+
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+			/* replicator output ports */
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+			port@0 {
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+				reg = <0>;
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+				replicator_out_port0: endpoint {
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+					remote-endpoint = <&tpiu_in_port>;
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+				};
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+			};
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+			port@1 {
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+				reg = <1>;
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+				replicator_out_port1: endpoint {
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+					remote-endpoint = <&etb_in_port>;
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+				};
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+			};
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+		};
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+		in-ports {
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+			/* replicator input port */
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+			port {
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+				replicator_in_port0: endpoint {
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+					remote-endpoint = <&funnel_out_port>;
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+				};
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+			};
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+		};
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+	};
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+
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 	amba: amba {
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 		compatible = "simple-bus";
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 		#address-cells = <1>;
..
..
@@ -219,7 +252,7 @@
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 			#size-cells = <0>;
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 		};
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-		sdhci0: sdhci@e0100000 {
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+		sdhci0: mmc@e0100000 {
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 			compatible = "arasan,sdhci-8.9a";
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 			status = "disabled";
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 			clock-names = "clk_xin", "clk_ahb";
..
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@@ -229,7 +262,7 @@
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 			reg = <0xe0100000 0x1000>;
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 		};
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-		sdhci1: sdhci@e0101000 {
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+		sdhci1: mmc@e0101000 {
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 			compatible = "arasan,sdhci-8.9a";
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 			status = "disabled";
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 			clock-names = "clk_xin", "clk_ahb";
..
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@@ -365,5 +398,107 @@
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 			reg = <0xf8005000 0x1000>;
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 			timeout-sec = <10>;
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 		};
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+
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+		etb@f8801000 {
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+			compatible = "arm,coresight-etb10", "arm,primecell";
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+			reg = <0xf8801000 0x1000>;
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+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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+			in-ports {
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+				port {
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+					etb_in_port: endpoint {
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+						remote-endpoint = <&replicator_out_port1>;
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+					};
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+				};
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+			};
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+		};
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+
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+		tpiu@f8803000 {
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+			compatible = "arm,coresight-tpiu", "arm,primecell";
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+			reg = <0xf8803000 0x1000>;
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+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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+			in-ports {
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+				port {
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+					tpiu_in_port: endpoint {
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+						remote-endpoint = <&replicator_out_port0>;
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+					};
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+				};
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+			};
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+		};
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+
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+		funnel@f8804000 {
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+			compatible = "arm,coresight-static-funnel", "arm,primecell";
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+			reg = <0xf8804000 0x1000>;
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+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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+
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+			/* funnel output ports */
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+			out-ports {
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+				port {
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+					funnel_out_port: endpoint {
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+						remote-endpoint =
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+							<&replicator_in_port0>;
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+					};
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+				};
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+			};
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+
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+			in-ports {
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				/* funnel input ports */
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+				port@0 {
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+					reg = <0>;
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+					funnel0_in_port0: endpoint {
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+						remote-endpoint = <&ptm0_out_port>;
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+					};
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+				};
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+
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+				port@1 {
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+					reg = <1>;
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+					funnel0_in_port1: endpoint {
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+						remote-endpoint = <&ptm1_out_port>;
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+					};
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+				};
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+
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+				port@2 {
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+					reg = <2>;
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+					funnel0_in_port2: endpoint {
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+					};
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+				};
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+				/* The other input ports are not connect to anything */
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+			};
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+		};
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+
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+		ptm@f889c000 {
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+			compatible = "arm,coresight-etm3x", "arm,primecell";
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+			reg = <0xf889c000 0x1000>;
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+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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+			cpu = <&cpu0>;
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+			out-ports {
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+				port {
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+					ptm0_out_port: endpoint {
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+						remote-endpoint = <&funnel0_in_port0>;
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+					};
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+				};
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+			};
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+		};
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+
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+		ptm@f889d000 {
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+			compatible = "arm,coresight-etm3x", "arm,primecell";
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+			reg = <0xf889d000 0x1000>;
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+			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
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+			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
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+			cpu = <&cpu1>;
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+			out-ports {
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+				port {
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+					ptm1_out_port: endpoint {
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+						remote-endpoint = <&funnel0_in_port1>;
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+					};
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+				};
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+			};
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+		};
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 	};
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 };