add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/vexpress-v2m.dtsi
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@@ -19,7 +19,7 @@
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  */
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 / {
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-	smb@4000000 {
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+	bus@40000000 {
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 		motherboard {
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 			model = "V2M-P1";
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 			arm,hbi = <0x190>;
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@@ -35,17 +35,15 @@
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 				reg = <0 0x00000000 0x04000000>,
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 				      <1 0x00000000 0x04000000>;
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 				bank-width = <4>;
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+				partitions {
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+					compatible = "arm,arm-firmware-suite";
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+				};
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 			};
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 			psram@2,00000000 {
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 				compatible = "arm,vexpress-psram", "mtd-ram";
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 				reg = <2 0x00000000 0x02000000>;
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 				bank-width = <4>;
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-			};
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-
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-			v2m_video_ram: vram@3,00000000 {
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-				compatible = "arm,vexpress-vram";
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-				reg = <3 0x00000000 0x00800000>;
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 			};
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 			ethernet@3,02000000 {
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@@ -138,7 +136,7 @@
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 				mmci@5000 {
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 					compatible = "arm,pl180", "arm,primecell";
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 					reg = <0x05000 0x1000>;
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-					interrupts = <9 10>;
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+					interrupts = <9>, <10>;
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 					cd-gpios = <&v2m_mmc_gpios 0 0>;
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 					wp-gpios = <&v2m_mmc_gpios 1 0>;
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 					max-frequency = <12000000>;
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@@ -200,7 +198,7 @@
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 					reg = <0x0f000 0x1000>;
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 					interrupts = <0>;
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 					clocks = <&v2m_refclk32khz>, <&smbclk>;
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-					clock-names = "wdogclk", "apb_pclk";
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+					clock-names = "wdog_clk", "apb_pclk";
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 				};
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 				v2m_timer01: timer@11000 {
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@@ -223,13 +221,37 @@
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 				v2m_i2c_dvi: i2c@16000 {
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 					compatible = "arm,versatile-i2c";
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 					reg = <0x16000 0x1000>;
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-
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 					#address-cells = <1>;
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 					#size-cells = <0>;
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 					dvi-transmitter@39 {
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 						compatible = "sil,sii9022-tpi", "sil,sii9022";
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 						reg = <0x39>;
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+
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+						ports {
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+							#address-cells = <1>;
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+							#size-cells = <0>;
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+
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+							/*
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+							 * Both the core tile and the motherboard routes their output
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+							 * pads to this transmitter. The motherboard system controller
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+							 * can select one of them as input using a mux register in
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+							 * "arm,vexpress-muxfpga". The Vexpress with the CA9 core tile is
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+							 * the only platform with this specific set-up.
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+							 */
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+							port@0 {
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+								reg = <0>;
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+								dvi_bridge_in_ct: endpoint {
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+									remote-endpoint = <&clcd_pads_ct>;
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+								};
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+							};
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+							port@1 {
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+								reg = <1>;
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+								dvi_bridge_in_mb: endpoint {
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+									remote-endpoint = <&clcd_pads_mb>;
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+								};
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+							};
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+						};
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 					};
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 					dvi-transmitter@60 {
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@@ -253,6 +275,7 @@
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 					reg-shift = <2>;
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 				};
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+
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 				clcd@1f000 {
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 					compatible = "arm,pl111", "arm,primecell";
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 					reg = <0x1f000 0x1000>;
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@@ -260,35 +283,14 @@
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 					interrupts = <14>;
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 					clocks = <&v2m_oscclk1>, <&smbclk>;
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 					clock-names = "clcdclk", "apb_pclk";
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-					memory-region = <&v2m_video_ram>;
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-					max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
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+					/* 800x600 16bpp @36MHz works fine */
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+					max-memory-bandwidth = <54000000>;
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+					memory-region = <&vram>;
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 					port {
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-						v2m_clcd_pads: endpoint {
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-							remote-endpoint = <&v2m_clcd_panel>;
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+						clcd_pads_mb: endpoint {
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+							remote-endpoint = <&dvi_bridge_in_mb>;
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 							arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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-						};
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-					};
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-
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-					panel {
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-						compatible = "panel-dpi";
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-
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-						port {
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-							v2m_clcd_panel: endpoint {
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-								remote-endpoint = <&v2m_clcd_pads>;
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-							};
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-						};
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-
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-						panel-timing {
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-							clock-frequency = <25175000>;
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-							hactive = <640>;
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-							hback-porch = <40>;
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-							hfront-porch = <24>;
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-							hsync-len = <96>;
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-							vactive = <480>;
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-							vback-porch = <32>;
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-							vfront-porch = <11>;
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-							vsync-len = <2>;
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 						};
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 					};
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 				};
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@@ -449,4 +451,4 @@
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 			};
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 		};
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 	};
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-};
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+};