add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/uniphier-pro4.dtsi
..
..
@@ -59,7 +59,7 @@
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 		ranges;
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 		interrupt-parent = <&intc>;
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61
 
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-		l2: l2-cache@500c0000 {
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+		l2: cache-controller@500c0000 {
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 			compatible = "socionext,uniphier-system-cache";
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 			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
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 			      <0x506c0000 0x400>;
..
..
@@ -69,6 +69,19 @@
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 			cache-sets = <256>;
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 			cache-line-size = <128>;
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 			cache-level = <2>;
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+		};
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+
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+		spi0: spi@54006000 {
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+			compatible = "socionext,uniphier-scssi";
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+			status = "disabled";
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+			reg = <0x54006000 0x100>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+			interrupts = <0 39 4>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&pinctrl_spi0>;
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+			clocks = <&peri_clk 11>;
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+			resets = <&peri_rst 11>;
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 		};
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86
 
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 		serial0: serial@54006800 {
..
..
@@ -258,6 +271,70 @@
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 			};
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 		};
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273
 
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+		dmac: dma-controller@5a000000 {
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+			compatible = "socionext,uniphier-mio-dmac";
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+			reg = <0x5a000000 0x1000>;
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+			interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
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+				     <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
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+			clocks = <&mio_clk 7>;
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+			resets = <&mio_rst 7>;
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+			#dma-cells = <1>;
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+		};
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+
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+		sd: mmc@5a400000 {
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+			compatible = "socionext,uniphier-sd-v2.91";
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+			status = "disabled";
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+			reg = <0x5a400000 0x200>;
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+			interrupts = <0 76 4>;
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+			pinctrl-names = "default", "uhs";
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+			pinctrl-0 = <&pinctrl_sd>;
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+			pinctrl-1 = <&pinctrl_sd_uhs>;
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+			clocks = <&mio_clk 0>;
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+			reset-names = "host", "bridge";
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+			resets = <&mio_rst 0>, <&mio_rst 3>;
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+			dma-names = "rx-tx";
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+			dmas = <&dmac 4>;
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+			bus-width = <4>;
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+			cap-sd-highspeed;
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+			sd-uhs-sdr12;
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+			sd-uhs-sdr25;
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+			sd-uhs-sdr50;
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+		};
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+
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+		emmc: mmc@5a500000 {
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+			compatible = "socionext,uniphier-sd-v2.91";
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+			status = "disabled";
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+			reg = <0x5a500000 0x200>;
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+			interrupts = <0 78 4>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&pinctrl_emmc>;
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+			clocks = <&mio_clk 1>;
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+			reset-names = "host", "bridge", "hw";
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+			resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
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+			dma-names = "rx-tx";
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+			dmas = <&dmac 5>;
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+			bus-width = <8>;
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+			cap-mmc-highspeed;
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+			cap-mmc-hw-reset;
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+			non-removable;
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+		};
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+
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+		sd1: mmc@5a600000 {
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+			compatible = "socionext,uniphier-sd-v2.91";
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+			status = "disabled";
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+			reg = <0x5a600000 0x200>;
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+			interrupts = <0 85 4>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&pinctrl_sd1>;
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+			clocks = <&mio_clk 2>;
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+			reset-names = "host", "bridge";
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+			resets = <&mio_rst 2>, <&mio_rst 5>;
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+			dma-names = "rx-tx";
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+			dmas = <&dmac 6>;
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+			bus-width = <4>;
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+			cap-sd-highspeed;
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+		};
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+
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 		usb2: usb@5a800100 {
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 			compatible = "socionext,uniphier-ehci", "generic-ehci";
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 			status = "disabled";
..
..
@@ -269,6 +346,8 @@
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 				 <&mio_clk 12>;
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 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
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 				 <&mio_rst 12>;
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+			phy-names = "usb";
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+			phys = <&usb_phy0>;
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 			has-transaction-translator;
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 		};
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353
 
..
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@@ -283,6 +362,8 @@
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 				 <&mio_clk 13>;
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 			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
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 				 <&mio_rst 13>;
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+			phy-names = "usb";
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+			phys = <&usb_phy1>;
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 			has-transaction-translator;
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 		};
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369
 
..
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@@ -293,6 +374,34 @@
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 			pinctrl: pinctrl {
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 				compatible = "socionext,uniphier-pro4-pinctrl";
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+			};
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+
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+			usb-phy {
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+				compatible = "socionext,uniphier-pro4-usb2-phy";
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
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+				usb_phy0: phy@0 {
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+					reg = <0>;
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+					#phy-cells = <0>;
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+				};
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+
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+				usb_phy1: phy@1 {
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+					reg = <1>;
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+					#phy-cells = <0>;
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+				};
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+
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+				usb_phy2: phy@2 {
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+					reg = <2>;
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+					#phy-cells = <0>;
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+					vbus-supply = <&usb0_vbus>;
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+				};
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+
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+				usb_phy3: phy@3 {
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+					reg = <3>;
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+					#phy-cells = <0>;
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+					vbus-supply = <&usb1_vbus>;
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+				};
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 			};
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 		};
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..
..
@@ -319,7 +428,15 @@
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 			};
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 		};
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-		aidet: aidet@5fc20000 {
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+		xdmac: dma-controller@5fc10000 {
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+			compatible = "socionext,uniphier-xdmac";
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+			reg = <0x5fc10000 0x5300>;
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+			interrupts = <0 188 4>;
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+			dma-channels = <16>;
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+			#dma-cells = <2>;
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+		};
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+
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+		aidet: interrupt-controller@5fc20000 {
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 			compatible = "socionext,uniphier-pro4-aidet";
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 			reg = <0x5fc20000 0x200>;
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 			interrupt-controller;
..
..
@@ -386,16 +503,115 @@
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 			};
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 		};
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505
 
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-		nand: nand@68000000 {
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+		usb0: usb@65a00000 {
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+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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+			status = "disabled";
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+			reg = <0x65a00000 0xcd00>;
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+			interrupt-names = "host", "peripheral";
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+			interrupts = <0 134 4>, <0 135 4>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&pinctrl_usb0>;
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+			clock-names = "ref", "bus_early", "suspend";
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+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
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+			resets = <&usb0_rst 4>;
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+			phys = <&usb_phy2>, <&usb0_ssphy>;
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+			dr_mode = "host";
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+		};
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+
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+		usb-glue@65b00000 {
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+			compatible = "socionext,uniphier-pro4-dwc3-glue",
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+				     "simple-mfd";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0 0x65b00000 0x100>;
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+
528
+			usb0_vbus: regulator@0 {
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+				compatible = "socionext,uniphier-pro4-usb3-regulator";
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+				reg = <0 0x10>;
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+				clock-names = "gio", "link";
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+				clocks = <&sys_clk 12>, <&sys_clk 14>;
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+				reset-names = "gio", "link";
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+				resets = <&sys_rst 12>, <&sys_rst 14>;
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+			};
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+
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+			usb0_ssphy: ss-phy@10 {
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+				compatible = "socionext,uniphier-pro4-usb3-ssphy";
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+				reg = <0x10 0x10>;
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+				#phy-cells = <0>;
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+				clock-names = "gio", "link";
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+				clocks = <&sys_clk 12>, <&sys_clk 14>;
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+				reset-names = "gio", "link";
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+				resets = <&sys_rst 12>, <&sys_rst 14>;
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+				vbus-supply = <&usb0_vbus>;
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+			};
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+
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+			usb0_rst: reset@40 {
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+				compatible = "socionext,uniphier-pro4-usb3-reset";
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+				reg = <0x40 0x4>;
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+				#reset-cells = <1>;
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+				clock-names = "gio", "link";
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+				clocks = <&sys_clk 12>, <&sys_clk 14>;
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+				reset-names = "gio", "link";
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+				resets = <&sys_rst 12>, <&sys_rst 14>;
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+			};
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+		};
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+
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+		usb1: usb@65c00000 {
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+			compatible = "socionext,uniphier-dwc3", "snps,dwc3";
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+			status = "disabled";
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+			reg = <0x65c00000 0xcd00>;
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+			interrupt-names = "host", "peripheral";
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+			interrupts = <0 137 4>, <0 138 4>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&pinctrl_usb1>;
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+			clock-names = "ref", "bus_early", "suspend";
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+			clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
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+			resets = <&usb1_rst 4>;
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+			phys = <&usb_phy3>;
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+			dr_mode = "host";
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+		};
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+
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+		usb-glue@65d00000 {
575
+			compatible = "socionext,uniphier-pro4-dwc3-glue",
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+				     "simple-mfd";
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges = <0 0x65d00000 0x100>;
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+
581
+			usb1_vbus: regulator@0 {
582
+				compatible = "socionext,uniphier-pro4-usb3-regulator";
583
+				reg = <0 0x10>;
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+				clock-names = "gio", "link";
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+				clocks = <&sys_clk 12>, <&sys_clk 15>;
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+				reset-names = "gio", "link";
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+				resets = <&sys_rst 12>, <&sys_rst 15>;
588
+			};
589
+
590
+			usb1_rst: reset@40 {
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+				compatible = "socionext,uniphier-pro4-usb3-reset";
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+				reg = <0x40 0x4>;
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+				#reset-cells = <1>;
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+				clock-names = "gio", "link";
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+				clocks = <&sys_clk 12>, <&sys_clk 15>;
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+				reset-names = "gio", "link";
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+				resets = <&sys_rst 12>, <&sys_rst 15>;
598
+			};
599
+		};
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+
601
+		nand: nand-controller@68000000 {
390
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 			compatible = "socionext,uniphier-denali-nand-v5a";
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 			status = "disabled";
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 			reg-names = "nand_data", "denali_reg";
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 			reg = <0x68000000 0x20>, <0x68100000 0x1000>;
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+			#address-cells = <1>;
607
+			#size-cells = <0>;
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608
 			interrupts = <0 65 4>;
395
609
 			pinctrl-names = "default";
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610
 			pinctrl-0 = <&pinctrl_nand>;
397
-			clocks = <&sys_clk 2>;
398
-			resets = <&sys_rst 2>;
611
+			clock-names = "nand", "nand_x", "ecc";
612
+			clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
613
+			reset-names = "nand", "reg";
614
+			resets = <&sys_rst 2>, <&sys_rst 2>;
399
615
 		};
400
616
 	};
401
617
 };