forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/tegra30.dtsi
....@@ -4,6 +4,7 @@
44 #include <dt-bindings/memory/tegra30-mc.h>
55 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
66 #include <dt-bindings/interrupt-controller/arm-gic.h>
7
+#include <dt-bindings/soc/tegra-pmc.h>
78 
89 / {
910 	compatible = "nvidia,tegra30";
....@@ -19,12 +20,12 @@
1920 	pcie@3000 {
2021 		compatible = "nvidia,tegra30-pcie";
2122 		device_type = "pci";
22
-		reg = <0x00003000 0x00000800   /* PADS registers */
23
-		       0x00003800 0x00000200   /* AFI registers */
24
-		       0x10000000 0x10000000>; /* configuration space */
23
+		reg = <0x00003000 0x00000800>, /* PADS registers */
24
+		      <0x00003800 0x00000200>, /* AFI registers */
25
+		      <0x10000000 0x10000000>; /* configuration space */
2526 		reg-names = "pads", "afi", "cs";
26
-		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
27
-			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
28
+			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2829 		interrupt-names = "intr", "msi";
2930 
3031 		#interrupt-cells = <1>;
....@@ -35,12 +36,12 @@
3536 		#address-cells = <3>;
3637 		#size-cells = <2>;
3738 
38
-		ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000   /* port 0 configuration space */
39
-			  0x82000000 0 0x00001000 0x00001000 0 0x00001000   /* port 1 configuration space */
40
-			  0x82000000 0 0x00004000 0x00004000 0 0x00001000   /* port 2 configuration space */
41
-			  0x81000000 0 0          0x02000000 0 0x00010000   /* downstream I/O */
42
-			  0x82000000 0 0x20000000 0x20000000 0 0x08000000   /* non-prefetchable memory */
43
-			  0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
39
+		ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
40
+			 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
41
+			 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
42
+			 <0x01000000 0 0          0x02000000 0 0x00010000>, /* downstream I/O */
43
+			 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
44
+			 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
4445 
4546 		clocks = <&tegra_car TEGRA30_CLK_PCIE>,
4647 			 <&tegra_car TEGRA30_CLK_AFI>,
....@@ -96,25 +97,27 @@
9697 		};
9798 	};
9899 
99
-	iram@40000000 {
100
+	sram@40000000 {
100101 		compatible = "mmio-sram";
101102 		reg = <0x40000000 0x40000>;
102103 		#address-cells = <1>;
103104 		#size-cells = <1>;
104105 		ranges = <0 0x40000000 0x40000>;
105106 
106
-		vde_pool: vde@400 {
107
+		vde_pool: sram@400 {
107108 			reg = <0x400 0x3fc00>;
108109 			pool;
109110 		};
110111 	};
111112 
112113 	host1x@50000000 {
113
-		compatible = "nvidia,tegra30-host1x", "simple-bus";
114
+		compatible = "nvidia,tegra30-host1x";
114115 		reg = <0x50000000 0x00024000>;
115116 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
116117 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
118
+		interrupt-names = "syncpt", "host1x";
117119 		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
120
+		clock-names = "host1x";
118121 		resets = <&tegra_car 28>;
119122 		reset-names = "host1x";
120123 		iommus = <&mc TEGRA_SWGROUP_HC>;
....@@ -182,8 +185,8 @@
182185 		gr3d@54180000 {
183186 			compatible = "nvidia,tegra30-gr3d";
184187 			reg = <0x54180000 0x00040000>;
185
-			clocks = <&tegra_car TEGRA30_CLK_GR3D
186
-				  &tegra_car TEGRA30_CLK_GR3D2>;
188
+			clocks = <&tegra_car TEGRA30_CLK_GR3D>,
189
+				 <&tegra_car TEGRA30_CLK_GR3D2>;
187190 			clock-names = "3d", "3d2";
188191 			resets = <&tegra_car 24>,
189192 				 <&tegra_car 98>;
....@@ -194,7 +197,7 @@
194197 		};
195198 
196199 		dc@54200000 {
197
-			compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
200
+			compatible = "nvidia,tegra30-dc";
198201 			reg = <0x54200000 0x00040000>;
199202 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
200203 			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
....@@ -254,8 +257,21 @@
254257 		dsi@54300000 {
255258 			compatible = "nvidia,tegra30-dsi";
256259 			reg = <0x54300000 0x00040000>;
257
-			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
260
+			clocks = <&tegra_car TEGRA30_CLK_DSIA>,
261
+				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
262
+			clock-names = "dsi", "parent";
258263 			resets = <&tegra_car 48>;
264
+			reset-names = "dsi";
265
+			status = "disabled";
266
+		};
267
+
268
+		dsi@54400000 {
269
+			compatible = "nvidia,tegra30-dsi";
270
+			reg = <0x54400000 0x00040000>;
271
+			clocks = <&tegra_car TEGRA30_CLK_DSIB>,
272
+				 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
273
+			clock-names = "dsi", "parent";
274
+			resets = <&tegra_car 84>;
259275 			reset-names = "dsi";
260276 			status = "disabled";
261277 		};
....@@ -272,8 +288,8 @@
272288 
273289 	intc: interrupt-controller@50041000 {
274290 		compatible = "arm,cortex-a9-gic";
275
-		reg = <0x50041000 0x1000
276
-		       0x50040100 0x0100>;
291
+		reg = <0x50041000 0x1000>,
292
+		      <0x50040100 0x0100>;
277293 		interrupt-controller;
278294 		#interrupt-cells = <3>;
279295 		interrupt-parent = <&intc>;
....@@ -370,6 +386,17 @@
370386 		reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
371387 	};
372388 
389
+	actmon@6000c800 {
390
+		compatible = "nvidia,tegra30-actmon";
391
+		reg = <0x6000c800 0x400>;
392
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
393
+		clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
394
+			 <&tegra_car TEGRA30_CLK_EMC>;
395
+		clock-names = "actmon", "emc";
396
+		resets = <&tegra_car TEGRA30_CLK_ACTMON>;
397
+		reset-names = "actmon";
398
+	};
399
+
373400 	gpio: gpio@6000d000 {
374401 		compatible = "nvidia,tegra30-gpio";
375402 		reg = <0x6000d000 0x1000>;
....@@ -392,15 +419,15 @@
392419 
393420 	vde@6001a000 {
394421 		compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
395
-		reg = <0x6001a000 0x1000   /* Syntax Engine */
396
-		       0x6001b000 0x1000   /* Video Bitstream Engine */
397
-		       0x6001c000  0x100   /* Macroblock Engine */
398
-		       0x6001c200  0x100   /* Post-processing Engine */
399
-		       0x6001c400  0x100   /* Motion Compensation Engine */
400
-		       0x6001c600  0x100   /* Transform Engine */
401
-		       0x6001c800  0x100   /* Pixel prediction block */
402
-		       0x6001ca00  0x100   /* Video DMA */
403
-		       0x6001d800  0x400>; /* Video frame controls */
422
+		reg = <0x6001a000 0x1000>, /* Syntax Engine */
423
+		      <0x6001b000 0x1000>, /* Video Bitstream Engine */
424
+		      <0x6001c000  0x100>, /* Macroblock Engine */
425
+		      <0x6001c200  0x100>, /* Post-processing Engine */
426
+		      <0x6001c400  0x100>, /* Motion Compensation Engine */
427
+		      <0x6001c600  0x100>, /* Transform Engine */
428
+		      <0x6001c800  0x100>, /* Pixel prediction block */
429
+		      <0x6001ca00  0x100>, /* Video DMA */
430
+		      <0x6001d800  0x400>; /* Video frame controls */
404431 		reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
405432 			    "tfe", "ppb", "vdma", "frameid";
406433 		iram = <&vde_pool>; /* IRAM region */
....@@ -411,18 +438,19 @@
411438 		clocks = <&tegra_car TEGRA30_CLK_VDE>;
412439 		reset-names = "vde", "mc";
413440 		resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
441
+		iommus = <&mc TEGRA_SWGROUP_VDE>;
414442 	};
415443 
416444 	apbmisc@70000800 {
417445 		compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
418
-		reg = <0x70000800 0x64   /* Chip revision */
419
-		       0x70000008 0x04>; /* Strapping options */
446
+		reg = <0x70000800 0x64>, /* Chip revision */
447
+		      <0x70000008 0x04>; /* Strapping options */
420448 	};
421449 
422450 	pinmux: pinmux@70000868 {
423451 		compatible = "nvidia,tegra30-pinmux";
424
-		reg = <0x70000868 0xd4    /* Pad control registers */
425
-		       0x70003000 0x3e4>; /* Mux registers */
452
+		reg = <0x70000868 0x0d4>, /* Pad control registers */
453
+		      <0x70003000 0x3e4>; /* Mux registers */
426454 	};
427455 
428456 	/*
....@@ -702,11 +730,12 @@
702730 		status = "disabled";
703731 	};
704732 
705
-	pmc@7000e400 {
733
+	tegra_pmc: pmc@7000e400 {
706734 		compatible = "nvidia,tegra30-pmc";
707735 		reg = <0x7000e400 0x400>;
708736 		clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
709737 		clock-names = "pclk", "clk32k_in";
738
+		#clock-cells = <1>;
710739 	};
711740 
712741 	mc: memory-controller@7000f000 {
....@@ -719,6 +748,15 @@
719748 
720749 		#iommu-cells = <1>;
721750 		#reset-cells = <1>;
751
+	};
752
+
753
+	memory-controller@7000f400 {
754
+		compatible = "nvidia,tegra30-emc";
755
+		reg = <0x7000f400 0x400>;
756
+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
757
+		clocks = <&tegra_car TEGRA30_CLK_EMC>;
758
+
759
+		nvidia,memory-controller = <&mc>;
722760 	};
723761 
724762 	fuse@7000f800 {
....@@ -747,8 +785,8 @@
747785 
748786 	ahub@70080000 {
749787 		compatible = "nvidia,tegra30-ahub";
750
-		reg = <0x70080000 0x200
751
-		       0x70080200 0x100>;
788
+		reg = <0x70080000 0x200>,
789
+		      <0x70080200 0x100>;
752790 		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
753791 		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
754792 			 <&tegra_car TEGRA30_CLK_APBIF>;
....@@ -828,41 +866,45 @@
828866 		};
829867 	};
830868 
831
-	sdhci@78000000 {
832
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
869
+	mmc@78000000 {
870
+		compatible = "nvidia,tegra30-sdhci";
833871 		reg = <0x78000000 0x200>;
834872 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
835873 		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
874
+		clock-names = "sdhci";
836875 		resets = <&tegra_car 14>;
837876 		reset-names = "sdhci";
838877 		status = "disabled";
839878 	};
840879 
841
-	sdhci@78000200 {
842
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
880
+	mmc@78000200 {
881
+		compatible = "nvidia,tegra30-sdhci";
843882 		reg = <0x78000200 0x200>;
844883 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
845884 		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
885
+		clock-names = "sdhci";
846886 		resets = <&tegra_car 9>;
847887 		reset-names = "sdhci";
848888 		status = "disabled";
849889 	};
850890 
851
-	sdhci@78000400 {
852
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
891
+	mmc@78000400 {
892
+		compatible = "nvidia,tegra30-sdhci";
853893 		reg = <0x78000400 0x200>;
854894 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
855895 		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
896
+		clock-names = "sdhci";
856897 		resets = <&tegra_car 69>;
857898 		reset-names = "sdhci";
858899 		status = "disabled";
859900 	};
860901 
861
-	sdhci@78000600 {
862
-		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
902
+	mmc@78000600 {
903
+		compatible = "nvidia,tegra30-sdhci";
863904 		reg = <0x78000600 0x200>;
864905 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
865906 		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
907
+		clock-names = "sdhci";
866908 		resets = <&tegra_car 15>;
867909 		reset-names = "sdhci";
868910 		status = "disabled";
....@@ -883,7 +925,8 @@
883925 
884926 	phy1: usb-phy@7d000000 {
885927 		compatible = "nvidia,tegra30-usb-phy";
886
-		reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
928
+		reg = <0x7d000000 0x4000>,
929
+		      <0x7d000000 0x4000>;
887930 		phy_type = "utmi";
888931 		clocks = <&tegra_car TEGRA30_CLK_USBD>,
889932 			 <&tegra_car TEGRA30_CLK_PLL_U>,
....@@ -891,6 +934,7 @@
891934 		clock-names = "reg", "pll_u", "utmi-pads";
892935 		resets = <&tegra_car 22>, <&tegra_car 22>;
893936 		reset-names = "usb", "utmi-pads";
937
+		#phy-cells = <0>;
894938 		nvidia,hssync-start-delay = <9>;
895939 		nvidia,idle-wait-delay = <17>;
896940 		nvidia,elastic-limit = <16>;
....@@ -920,7 +964,8 @@
920964 
921965 	phy2: usb-phy@7d004000 {
922966 		compatible = "nvidia,tegra30-usb-phy";
923
-		reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
967
+		reg = <0x7d004000 0x4000>,
968
+		      <0x7d000000 0x4000>;
924969 		phy_type = "utmi";
925970 		clocks = <&tegra_car TEGRA30_CLK_USB2>,
926971 			 <&tegra_car TEGRA30_CLK_PLL_U>,
....@@ -928,6 +973,7 @@
928973 		clock-names = "reg", "pll_u", "utmi-pads";
929974 		resets = <&tegra_car 58>, <&tegra_car 22>;
930975 		reset-names = "usb", "utmi-pads";
976
+		#phy-cells = <0>;
931977 		nvidia,hssync-start-delay = <9>;
932978 		nvidia,idle-wait-delay = <17>;
933979 		nvidia,elastic-limit = <16>;
....@@ -956,7 +1002,8 @@
9561002 
9571003 	phy3: usb-phy@7d008000 {
9581004 		compatible = "nvidia,tegra30-usb-phy";
959
-		reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
1005
+		reg = <0x7d008000 0x4000>,
1006
+		      <0x7d000000 0x4000>;
9601007 		phy_type = "utmi";
9611008 		clocks = <&tegra_car TEGRA30_CLK_USB3>,
9621009 			 <&tegra_car TEGRA30_CLK_PLL_U>,
....@@ -964,6 +1011,7 @@
9641011 		clock-names = "reg", "pll_u", "utmi-pads";
9651012 		resets = <&tegra_car 59>, <&tegra_car 22>;
9661013 		reset-names = "usb", "utmi-pads";
1014
+		#phy-cells = <0>;
9671015 		nvidia,hssync-start-delay = <0>;
9681016 		nvidia,idle-wait-delay = <17>;
9691017 		nvidia,elastic-limit = <16>;
....@@ -986,24 +1034,28 @@
9861034 			device_type = "cpu";
9871035 			compatible = "arm,cortex-a9";
9881036 			reg = <0>;
1037
+			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
9891038 		};
9901039 
9911040 		cpu@1 {
9921041 			device_type = "cpu";
9931042 			compatible = "arm,cortex-a9";
9941043 			reg = <1>;
1044
+			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
9951045 		};
9961046 
9971047 		cpu@2 {
9981048 			device_type = "cpu";
9991049 			compatible = "arm,cortex-a9";
10001050 			reg = <2>;
1051
+			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
10011052 		};
10021053 
10031054 		cpu@3 {
10041055 			device_type = "cpu";
10051056 			compatible = "arm,cortex-a9";
10061057 			reg = <3>;
1058
+			clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
10071059 		};
10081060 	};
10091061 
....@@ -1013,5 +1065,9 @@
10131065 			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
10141066 			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
10151067 			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1068
+		interrupt-affinity = <&{/cpus/cpu@0}>,
1069
+				     <&{/cpus/cpu@1}>,
1070
+				     <&{/cpus/cpu@2}>,
1071
+				     <&{/cpus/cpu@3}>;
10161072 	};
10171073 };