add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/tegra20-paz00.dts
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@@ -3,6 +3,8 @@
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3
 
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 #include <dt-bindings/input/input.h>
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 #include "tegra20.dtsi"
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+#include "tegra20-cpu-opp.dtsi"
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+#include "tegra20-cpu-opp-microvolt.dtsi"
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 / {
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 	model = "Toshiba AC100 / Dynabook AZ";
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@@ -303,10 +305,56 @@
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 		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
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 		slave-addr = <138>;
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 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
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-		         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
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+			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
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 		clock-names = "div-clk", "fast-clk";
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 		resets = <&tegra_car 67>;
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 		reset-names = "i2c";
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+	};
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+
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+	memory-controller@7000f400 {
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+		nvidia,use-ram-code;
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+
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+		emc-tables@0 {
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+			nvidia,ram-code = <0x0>;
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+
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+			emc-table@166500 {
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+				reg = <166500>;
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+				compatible = "nvidia,tegra20-emc-table";
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+				clock-frequency = <166500>;
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+				nvidia,emc-registers = <0x0000000a 0x00000016
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+					0x00000008 0x00000003 0x00000004 0x00000004
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+					0x00000002 0x0000000c 0x00000003 0x00000003
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+					0x00000002 0x00000001 0x00000004 0x00000005
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+					0x00000004 0x00000009 0x0000000d 0x000004df
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+					0x00000000 0x00000003 0x00000003 0x00000003
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+					0x00000003 0x00000001 0x0000000a 0x000000c8
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+					0x00000003 0x00000006 0x00000004 0x00000008
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+					0x00000002 0x00000000 0x00000000 0x00000002
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+					0x00000000 0x00000000 0x00000083 0xe03b0323
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+					0x007fe010 0x00001414 0x00000000 0x00000000
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+					0x00000000 0x00000000 0x00000000 0x00000000>;
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+			};
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+
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+			emc-table@333000 {
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+				reg = <333000>;
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+				compatible = "nvidia,tegra20-emc-table";
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+				clock-frequency = <333000>;
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+				nvidia,emc-registers = <0x00000018 0x00000033
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+					0x00000012 0x00000004 0x00000004 0x00000005
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+					0x00000003 0x0000000c 0x00000006 0x00000006
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+					0x00000003 0x00000001 0x00000004 0x00000005
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+					0x00000004 0x00000009 0x0000000d 0x00000bff
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+					0x00000000 0x00000003 0x00000003 0x00000006
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+					0x00000006 0x00000001 0x00000011 0x000000c8
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+					0x00000003 0x0000000e 0x00000007 0x00000008
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+					0x00000002 0x00000000 0x00000000 0x00000002
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+					0x00000000 0x00000000 0x00000083 0xf0440303
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+					0x007fe010 0x00001414 0x00000000 0x00000000
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+					0x00000000 0x00000000 0x00000000 0x00000000>;
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+			};
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+		};
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 	};
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 	i2c@7000d000 {
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@@ -337,18 +385,26 @@
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 					regulator-always-on;
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 				};
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-				sm0 {
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+				core_vdd_reg: sm0 {
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 					regulator-name = "+1.2vs_sm0,vdd_core";
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 					regulator-min-microvolt = <1200000>;
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-					regulator-max-microvolt = <1200000>;
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+					regulator-max-microvolt = <1225000>;
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+					regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
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+					regulator-coupled-max-spread = <170000 450000>;
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 					regulator-always-on;
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+
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+					nvidia,tegra-core-regulator;
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 				};
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-				sm1 {
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+				cpu_vdd_reg: sm1 {
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 					regulator-name = "+1.0vs_sm1,vdd_cpu";
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-					regulator-min-microvolt = <1000000>;
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-					regulator-max-microvolt = <1000000>;
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+					regulator-min-microvolt = <750000>;
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+					regulator-max-microvolt = <1100000>;
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+					regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
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+					regulator-coupled-max-spread = <450000 450000>;
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 					regulator-always-on;
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+
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+					nvidia,tegra-cpu-regulator;
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 				};
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 				sm2_reg: sm2 {
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@@ -367,10 +423,15 @@
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 					regulator-always-on;
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 				};
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-				ldo2 {
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+				rtc_vdd_reg: ldo2 {
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 					regulator-name = "+1.2vs_ldo2,vdd_rtc";
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 					regulator-min-microvolt = <1200000>;
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-					regulator-max-microvolt = <1200000>;
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+					regulator-max-microvolt = <1225000>;
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+					regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
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+					regulator-coupled-max-spread = <170000 450000>;
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+					regulator-always-on;
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+
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+					nvidia,tegra-rtc-regulator;
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 				};
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 				ldo3 {
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@@ -482,7 +543,7 @@
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 		status = "okay";
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 	};
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-	sdhci@c8000000 {
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+	mmc@c8000000 {
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 		status = "okay";
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 		cd-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_LOW>;
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 		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
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@@ -490,7 +551,7 @@
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 		bus-width = <4>;
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 	};
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-	sdhci@c8000600 {
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+	mmc@c8000600 {
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 		status = "okay";
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 		bus-width = <8>;
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 		non-removable;
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@@ -508,17 +569,10 @@
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 		backlight-boot-off;
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 	};
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-	clocks {
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-		compatible = "simple-bus";
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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-
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-		clk32k_in: clock@0 {
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-			compatible = "fixed-clock";
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-			reg = <0>;
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-			#clock-cells = <0>;
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-			clock-frequency = <32768>;
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-		};
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+	clk32k_in: clock@0 {
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+		compatible = "fixed-clock";
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+		clock-frequency = <32768>;
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+		#clock-cells = <0>;
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 	};
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 	gpio-keys {
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@@ -535,7 +589,7 @@
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 	gpio-leds {
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 		compatible = "gpio-leds";
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591
 
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-		wifi {
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+		led-0 {
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 			label = "wifi-led";
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 			gpios = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
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 			linux,default-trigger = "rfkill0";
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@@ -543,7 +597,7 @@
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 	};
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 	panel: panel {
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-		compatible = "samsung,ltn101nt05", "simple-panel";
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+		compatible = "samsung,ltn101nt05";
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 		ddc-i2c-bus = <&lvds_ddc>;
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 		power-supply = <&vdd_pnl_reg>;
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@@ -552,30 +606,22 @@
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 		backlight = <&backlight>;
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 	};
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-	regulators {
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-		compatible = "simple-bus";
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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+	p5valw_reg: regulator@0 {
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+		compatible = "regulator-fixed";
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+		regulator-name = "+5valw";
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+		regulator-min-microvolt = <5000000>;
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+		regulator-max-microvolt = <5000000>;
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+		regulator-always-on;
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+	};
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-		p5valw_reg: regulator@0 {
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-			compatible = "regulator-fixed";
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-			reg = <0>;
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-			regulator-name = "+5valw";
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-			regulator-min-microvolt = <5000000>;
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-			regulator-max-microvolt = <5000000>;
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-			regulator-always-on;
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-		};
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-
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-		vdd_pnl_reg: regulator@1 {
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-			compatible = "regulator-fixed";
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-			reg = <1>;
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-			regulator-name = "+3VS,vdd_pnl";
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-			regulator-min-microvolt = <3300000>;
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-			regulator-max-microvolt = <3300000>;
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-			regulator-boot-on;
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-			gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
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-			enable-active-high;
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-		};
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+	vdd_pnl_reg: regulator@1 {
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+		compatible = "regulator-fixed";
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+		regulator-name = "+3VS,vdd_pnl";
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+		regulator-min-microvolt = <3300000>;
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+		regulator-max-microvolt = <3300000>;
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+		regulator-boot-on;
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+		gpio = <&gpio TEGRA_GPIO(A, 4) GPIO_ACTIVE_HIGH>;
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+		enable-active-high;
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 	};
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626
 
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 	sound {
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@@ -599,8 +645,20 @@
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 			GPIO_ACTIVE_HIGH>;
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 		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
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-		         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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-		         <&tegra_car TEGRA20_CLK_CDEV1>;
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+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
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+			 <&tegra_car TEGRA20_CLK_CDEV1>;
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 		clock-names = "pll_a", "pll_a_out0", "mclk";
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 	};
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+
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+	cpus {
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+		cpu0: cpu@0 {
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+			cpu-supply = <&cpu_vdd_reg>;
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+			operating-points-v2 = <&cpu0_opp_table>;
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+		};
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+
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+		cpu@1 {
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+			cpu-supply = <&cpu_vdd_reg>;
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+			operating-points-v2 = <&cpu0_opp_table>;
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+		};
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+	};
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 };