add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/tegra124.dtsi
..
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@@ -6,6 +6,7 @@
6
6
 #include <dt-bindings/interrupt-controller/arm-gic.h>
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 #include <dt-bindings/reset/tegra124-car.h>
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 #include <dt-bindings/thermal/tegra124-soctherm.h>
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+#include <dt-bindings/soc/tegra-pmc.h>
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10
 
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 / {
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 	compatible = "nvidia,tegra124";
..
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@@ -21,9 +22,9 @@
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 	pcie@1003000 {
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 		compatible = "nvidia,tegra124-pcie";
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 		device_type = "pci";
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-		reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
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-		       0x0 0x01003800 0x0 0x00000800   /* AFI registers */
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-		       0x0 0x02000000 0x0 0x10000000>; /* configuration space */
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+		reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
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+		      <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
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+		      <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
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 		reg-names = "pads", "afi", "cs";
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 		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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 			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
..
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@@ -37,11 +38,11 @@
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 		#address-cells = <3>;
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 		#size-cells = <2>;
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40
-		ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000   /* port 0 configuration space */
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-			  0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000   /* port 1 configuration space */
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-			  0x81000000 0 0x0        0x0 0x12000000 0 0x00010000   /* downstream I/O (64 KiB) */
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-			  0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000   /* non-prefetchable memory (208 MiB) */
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-			  0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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+		ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
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+			 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
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+			 <0x01000000 0 0x0        0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
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+			 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
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+			 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
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46
 
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 		clocks = <&tegra_car TEGRA124_CLK_PCIE>,
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 			 <&tegra_car TEGRA124_CLK_AFI>,
..
..
@@ -84,11 +85,13 @@
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 	};
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86
 
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 	host1x@50000000 {
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-		compatible = "nvidia,tegra124-host1x", "simple-bus";
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+		compatible = "nvidia,tegra124-host1x";
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 		reg = <0x0 0x50000000 0x0 0x00034000>;
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 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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+		interrupt-names = "syncpt", "host1x";
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 		clocks = <&tegra_car TEGRA124_CLK_HOST1X>;
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+		clock-names = "host1x";
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 		resets = <&tegra_car 28>;
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 		reset-names = "host1x";
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 		iommus = <&mc TEGRA_SWGROUP_HC>;
..
..
@@ -102,9 +105,8 @@
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 			compatible = "nvidia,tegra124-dc";
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 			reg = <0x0 0x54200000 0x0 0x00040000>;
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 			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&tegra_car TEGRA124_CLK_DISP1>,
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-				 <&tegra_car TEGRA124_CLK_PLL_P>;
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-			clock-names = "dc", "parent";
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+			clocks = <&tegra_car TEGRA124_CLK_DISP1>;
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+			clock-names = "dc";
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 			resets = <&tegra_car 27>;
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 			reset-names = "dc";
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..
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@@ -117,9 +119,8 @@
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 			compatible = "nvidia,tegra124-dc";
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 			reg = <0x0 0x54240000 0x0 0x00040000>;
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 			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&tegra_car TEGRA124_CLK_DISP2>,
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-				 <&tegra_car TEGRA124_CLK_PLL_P>;
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-			clock-names = "dc", "parent";
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+			clocks = <&tegra_car TEGRA124_CLK_DISP2>;
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+			clock-names = "dc";
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 			resets = <&tegra_car 26>;
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 			reset-names = "dc";
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..
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@@ -140,15 +141,28 @@
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 			status = "disabled";
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 		};
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+		vic@54340000 {
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+			compatible = "nvidia,tegra124-vic";
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+			reg = <0x0 0x54340000 0x0 0x00040000>;
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+			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&tegra_car TEGRA124_CLK_VIC03>;
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+			clock-names = "vic";
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+			resets = <&tegra_car 178>;
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+			reset-names = "vic";
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+
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+			iommus = <&mc TEGRA_SWGROUP_VIC>;
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+		};
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+
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 		sor@54540000 {
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 			compatible = "nvidia,tegra124-sor";
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 			reg = <0x0 0x54540000 0x0 0x00040000>;
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 			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
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+				 <&tegra_car TEGRA124_CLK_SOR0_OUT>,
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 				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
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 				 <&tegra_car TEGRA124_CLK_PLL_DP>,
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 				 <&tegra_car TEGRA124_CLK_CLK_M>;
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-			clock-names = "sor", "parent", "dp", "safe";
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+			clock-names = "sor", "out", "parent", "dp", "safe";
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 			resets = <&tegra_car 182>;
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 			reset-names = "sor";
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 			status = "disabled";
..
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@@ -164,6 +178,11 @@
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 			resets = <&tegra_car 181>;
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 			reset-names = "dpaux";
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 			status = "disabled";
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+
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+			i2c-bus {
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+			};
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 		};
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 	};
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..
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@@ -582,11 +601,12 @@
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 		clocks = <&tegra_car TEGRA124_CLK_RTC>;
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 	};
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-	pmc@7000e400 {
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+	tegra_pmc: pmc@7000e400 {
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 		compatible = "nvidia,tegra124-pmc";
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 		reg = <0x0 0x7000e400 0x0 0x400>;
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 		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
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 		clock-names = "pclk", "clk32k_in";
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+		#clock-cells = <1>;
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 	};
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611
 
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 	fuse@7000f800 {
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@@ -607,11 +627,14 @@
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 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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 		#iommu-cells = <1>;
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+		#reset-cells = <1>;
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 	};
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632
 
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-	emc: emc@7001b000 {
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+	emc: external-memory-controller@7001b000 {
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 		compatible = "nvidia,tegra124-emc";
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 		reg = <0x0 0x7001b000 0x0 0x1000>;
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+		clocks = <&tegra_car TEGRA124_CLK_EMC>;
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+		clock-names = "emc";
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638
 
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 		nvidia,memory-controller = <&mc>;
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 	};
..
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@@ -662,8 +685,8 @@
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 			 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>,
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 			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
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 			 <&tegra_car TEGRA124_CLK_XUSB_SS>,
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-			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
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 			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
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+			 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>,
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 			 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>,
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 			 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>,
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 			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
..
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@@ -671,7 +694,7 @@
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 			 <&tegra_car TEGRA124_CLK_PLL_E>;
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 		clock-names = "xusb_host", "xusb_host_src",
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 			      "xusb_falcon_src", "xusb_ss",
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-			      "xusb_ss_div2", "xusb_ss_src",
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+			      "xusb_ss_src", "xusb_ss_div2",
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 			      "xusb_hs_src", "xusb_fs_src",
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 			      "pll_u_480m", "clk_m", "pll_e";
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 		resets = <&tegra_car 89>, <&tegra_car 156>,
..
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@@ -816,41 +839,45 @@
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 		};
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 	};
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819
-	sdhci@700b0000 {
842
+	mmc@700b0000 {
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 		compatible = "nvidia,tegra124-sdhci";
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 		reg = <0x0 0x700b0000 0x0 0x200>;
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 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 14>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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829
-	sdhci@700b0200 {
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+	mmc@700b0200 {
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 		compatible = "nvidia,tegra124-sdhci";
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 		reg = <0x0 0x700b0200 0x0 0x200>;
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 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 9>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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-	sdhci@700b0400 {
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+	mmc@700b0400 {
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 		compatible = "nvidia,tegra124-sdhci";
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 		reg = <0x0 0x700b0400 0x0 0x200>;
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 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 69>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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-	sdhci@700b0600 {
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+	mmc@700b0600 {
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 		compatible = "nvidia,tegra124-sdhci";
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 		reg = <0x0 0x700b0600 0x0 0x200>;
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 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 15>;
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 		reset-names = "sdhci";
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 		status = "disabled";
..
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@@ -868,8 +895,8 @@
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895
 
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 	soctherm: thermal-sensor@700e2000 {
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 		compatible = "nvidia,tegra124-soctherm";
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-		reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
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-			0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
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+		reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
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+		      <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
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 		reg-names = "soctherm-reg", "car-reg";
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 		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA124_CLK_TSENSOR>,
..
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@@ -1039,6 +1066,7 @@
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 		clock-names = "reg", "pll_u", "utmi-pads";
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 		resets = <&tegra_car 22>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
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+		#phy-cells = <0>;
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 		nvidia,hssync-start-delay = <0>;
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 		nvidia,idle-wait-delay = <17>;
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 		nvidia,elastic-limit = <16>;
..
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@@ -1076,6 +1104,7 @@
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 		clock-names = "reg", "pll_u", "utmi-pads";
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 		resets = <&tegra_car 58>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
1107
+		#phy-cells = <0>;
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 		nvidia,hssync-start-delay = <0>;
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 		nvidia,idle-wait-delay = <17>;
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 		nvidia,elastic-limit = <16>;
..
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@@ -1112,6 +1141,7 @@
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 		clock-names = "reg", "pll_u", "utmi-pads";
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 		resets = <&tegra_car 59>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
1144
+		#phy-cells = <0>;
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 		nvidia,hssync-start-delay = <0>;
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 		nvidia,idle-wait-delay = <17>;
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 		nvidia,elastic-limit = <16>;