.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0 OR X11 |
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1 | 2 | /* |
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2 | | - * Copyright 2016-2018 Toradex AG |
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3 | | - * |
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4 | | - * This file is dual-licensed: you can use it either under the terms |
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5 | | - * of the GPL or the X11 license, at your option. Note that this dual |
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6 | | - * licensing only applies to this file, and not this project as a |
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7 | | - * whole. |
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8 | | - * |
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9 | | - * a) This file is free software; you can redistribute it and/or |
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10 | | - * modify it under the terms of the GNU General Public License |
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11 | | - * version 2 as published by the Free Software Foundation. |
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12 | | - * |
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13 | | - * This file is distributed in the hope that it will be useful |
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14 | | - * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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15 | | - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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16 | | - * GNU General Public License for more details. |
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17 | | - * |
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18 | | - * Or, alternatively |
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19 | | - * |
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20 | | - * b) Permission is hereby granted, free of charge, to any person |
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21 | | - * obtaining a copy of this software and associated documentation |
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22 | | - * files (the "Software"), to deal in the Software without |
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23 | | - * restriction, including without limitation the rights to use |
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24 | | - * copy, modify, merge, publish, distribute, sublicense, and/or |
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25 | | - * sell copies of the Software, and to permit persons to whom the |
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26 | | - * Software is furnished to do so, subject to the following |
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27 | | - * conditions: |
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28 | | - * |
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29 | | - * The above copyright notice and this permission notice shall be |
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30 | | - * included in all copies or substantial portions of the Software. |
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31 | | - * |
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32 | | - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND |
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33 | | - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES |
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34 | | - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
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35 | | - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT |
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36 | | - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY |
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37 | | - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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38 | | - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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39 | | - * OTHER DEALINGS IN THE SOFTWARE. |
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| 3 | + * Copyright 2016-2019 Toradex AG |
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40 | 4 | */ |
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41 | 5 | |
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42 | 6 | #include "tegra124.dtsi" |
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.. | .. |
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47 | 11 | * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A |
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48 | 12 | */ |
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49 | 13 | / { |
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50 | | - model = "Toradex Apalis TK1"; |
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51 | | - compatible = "toradex,apalis-tk1", "nvidia,tegra124"; |
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52 | | - |
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53 | 14 | memory@80000000 { |
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54 | 15 | reg = <0x0 0x80000000 0x0 0x80000000>; |
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55 | 16 | }; |
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56 | 17 | |
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57 | 18 | pcie@1003000 { |
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58 | 19 | status = "okay"; |
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59 | | - avddio-pex-supply = <&vdd_1v05>; |
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60 | | - avdd-pex-pll-supply = <&vdd_1v05>; |
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61 | | - avdd-pll-erefe-supply = <&avdd_1v05>; |
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62 | | - dvddio-pex-supply = <&vdd_1v05>; |
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63 | | - hvdd-pex-pll-e-supply = <®_3v3>; |
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64 | | - hvdd-pex-supply = <®_3v3>; |
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65 | | - vddio-pex-ctl-supply = <®_3v3>; |
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| 20 | + avddio-pex-supply = <®_1v05_vdd>; |
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| 21 | + avdd-pex-pll-supply = <®_1v05_vdd>; |
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| 22 | + avdd-pll-erefe-supply = <®_1v05_avdd>; |
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| 23 | + dvddio-pex-supply = <®_1v05_vdd>; |
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| 24 | + hvdd-pex-pll-e-supply = <®_module_3v3>; |
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| 25 | + hvdd-pex-supply = <®_module_3v3>; |
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| 26 | + vddio-pex-ctl-supply = <®_module_3v3>; |
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66 | 27 | |
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67 | 28 | /* Apalis PCIe (additional lane Apalis type specific) */ |
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68 | 29 | pci@1,0 { |
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.. | .. |
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77 | 38 | phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; |
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78 | 39 | phy-names = "pcie-0"; |
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79 | 40 | status = "okay"; |
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| 41 | + |
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| 42 | + ethernet@0,0 { |
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| 43 | + reg = <0 0 0 0 0>; |
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| 44 | + local-mac-address = [00 00 00 00 00 00]; |
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| 45 | + }; |
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80 | 46 | }; |
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81 | 47 | }; |
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82 | 48 | |
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83 | 49 | host1x@50000000 { |
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84 | 50 | hdmi@54280000 { |
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85 | | - pll-supply = <®_1v05_avdd_hdmi_pll>; |
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86 | | - vdd-supply = <®_3v3_avdd_hdmi>; |
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87 | 51 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
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88 | 52 | nvidia,hpd-gpio = |
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89 | 53 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; |
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| 54 | + pll-supply = <®_1v05_avdd_hdmi_pll>; |
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| 55 | + vdd-supply = <®_3v3_avdd_hdmi>; |
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90 | 56 | }; |
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91 | 57 | }; |
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92 | 58 | |
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.. | .. |
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95 | 61 | * Node left disabled on purpose - the bootloader will enable |
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96 | 62 | * it after having set the VPR up |
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97 | 63 | */ |
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98 | | - vdd-supply = <&vdd_gpu>; |
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| 64 | + vdd-supply = <®_vdd_gpu>; |
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99 | 65 | }; |
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100 | 66 | |
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101 | | - pinmux: pinmux@70000868 { |
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| 67 | + pinmux@70000868 { |
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102 | 68 | pinctrl-names = "default"; |
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103 | 69 | pinctrl-0 = <&state_default>; |
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104 | 70 | |
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105 | 71 | state_default: pinmux { |
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106 | 72 | /* Analogue Audio (On-module) */ |
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107 | | - dap3_fs_pp0 { |
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| 73 | + dap3-fs-pp0 { |
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108 | 74 | nvidia,pins = "dap3_fs_pp0"; |
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109 | 75 | nvidia,function = "i2s2"; |
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110 | 76 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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111 | 77 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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112 | 78 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
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113 | 79 | }; |
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114 | | - dap3_din_pp1 { |
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| 80 | + dap3-din-pp1 { |
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115 | 81 | nvidia,pins = "dap3_din_pp1"; |
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116 | 82 | nvidia,function = "i2s2"; |
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117 | 83 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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118 | 84 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
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119 | 85 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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120 | 86 | }; |
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121 | | - dap3_dout_pp2 { |
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| 87 | + dap3-dout-pp2 { |
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122 | 88 | nvidia,pins = "dap3_dout_pp2"; |
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123 | 89 | nvidia,function = "i2s2"; |
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124 | 90 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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125 | 91 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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126 | 92 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
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127 | 93 | }; |
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128 | | - dap3_sclk_pp3 { |
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| 94 | + dap3-sclk-pp3 { |
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129 | 95 | nvidia,pins = "dap3_sclk_pp3"; |
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130 | 96 | nvidia,function = "i2s2"; |
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131 | 97 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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132 | 98 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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133 | 99 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
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134 | 100 | }; |
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135 | | - dap_mclk1_pw4 { |
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| 101 | + dap-mclk1-pw4 { |
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136 | 102 | nvidia,pins = "dap_mclk1_pw4"; |
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137 | 103 | nvidia,function = "extperiph1"; |
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138 | 104 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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159 | 125 | }; |
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160 | 126 | |
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161 | 127 | /* Apalis CAM1_MCLK */ |
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162 | | - cam_mclk_pcc0 { |
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| 128 | + cam-mclk-pcc0 { |
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163 | 129 | nvidia,pins = "cam_mclk_pcc0"; |
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164 | 130 | nvidia,function = "vi_alt3"; |
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165 | 131 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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168 | 134 | }; |
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169 | 135 | |
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170 | 136 | /* Apalis Digital Audio */ |
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171 | | - dap2_fs_pa2 { |
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| 137 | + dap2-fs-pa2 { |
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172 | 138 | nvidia,pins = "dap2_fs_pa2"; |
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173 | 139 | nvidia,function = "hda"; |
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174 | 140 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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175 | 141 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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176 | 142 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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177 | 143 | }; |
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178 | | - dap2_sclk_pa3 { |
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| 144 | + dap2-sclk-pa3 { |
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179 | 145 | nvidia,pins = "dap2_sclk_pa3"; |
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180 | 146 | nvidia,function = "hda"; |
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181 | 147 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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182 | 148 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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183 | 149 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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184 | 150 | }; |
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185 | | - dap2_din_pa4 { |
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| 151 | + dap2-din-pa4 { |
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186 | 152 | nvidia,pins = "dap2_din_pa4"; |
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187 | 153 | nvidia,function = "hda"; |
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188 | 154 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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189 | 155 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
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190 | 156 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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191 | 157 | }; |
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192 | | - dap2_dout_pa5 { |
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| 158 | + dap2-dout-pa5 { |
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193 | 159 | nvidia,pins = "dap2_dout_pa5"; |
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194 | 160 | nvidia,function = "hda"; |
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195 | 161 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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202 | 168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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203 | 169 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
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204 | 170 | }; |
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205 | | - clk3_out_pee0 { |
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| 171 | + clk3-out-pee0 { |
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206 | 172 | nvidia,pins = "clk3_out_pee0"; |
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207 | 173 | nvidia,function = "extperiph3"; |
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208 | 174 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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211 | 177 | }; |
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212 | 178 | |
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213 | 179 | /* Apalis GPIO */ |
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214 | | - ddc_scl_pv4 { |
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| 180 | + ddc-scl-pv4 { |
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215 | 181 | nvidia,pins = "ddc_scl_pv4"; |
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216 | 182 | nvidia,function = "rsvd2"; |
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217 | 183 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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218 | 184 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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219 | 185 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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220 | 186 | }; |
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221 | | - ddc_sda_pv5 { |
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| 187 | + ddc-sda-pv5 { |
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222 | 188 | nvidia,pins = "ddc_sda_pv5"; |
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223 | 189 | nvidia,function = "rsvd2"; |
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224 | 190 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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225 | 191 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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226 | 192 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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227 | 193 | }; |
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228 | | - pex_l0_rst_n_pdd1 { |
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| 194 | + pex-l0-rst-n-pdd1 { |
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229 | 195 | nvidia,pins = "pex_l0_rst_n_pdd1"; |
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230 | 196 | nvidia,function = "rsvd2"; |
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231 | 197 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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232 | 198 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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233 | 199 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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234 | 200 | }; |
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235 | | - pex_l0_clkreq_n_pdd2 { |
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| 201 | + pex-l0-clkreq-n-pdd2 { |
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236 | 202 | nvidia,pins = "pex_l0_clkreq_n_pdd2"; |
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237 | 203 | nvidia,function = "rsvd2"; |
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238 | 204 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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239 | 205 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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240 | 206 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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241 | 207 | }; |
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242 | | - pex_l1_rst_n_pdd5 { |
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| 208 | + pex-l1-rst-n-pdd5 { |
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243 | 209 | nvidia,pins = "pex_l1_rst_n_pdd5"; |
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244 | 210 | nvidia,function = "rsvd2"; |
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245 | 211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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246 | 212 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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247 | 213 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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248 | 214 | }; |
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249 | | - pex_l1_clkreq_n_pdd6 { |
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| 215 | + pex-l1-clkreq-n-pdd6 { |
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250 | 216 | nvidia,pins = "pex_l1_clkreq_n_pdd6"; |
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251 | 217 | nvidia,function = "rsvd2"; |
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252 | 218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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253 | 219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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254 | 220 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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255 | 221 | }; |
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256 | | - dp_hpd_pff0 { |
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| 222 | + dp-hpd-pff0 { |
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257 | 223 | nvidia,pins = "dp_hpd_pff0"; |
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258 | 224 | nvidia,function = "dp"; |
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259 | 225 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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277 | 243 | }; |
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278 | 244 | |
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279 | 245 | /* Apalis HDMI1_CEC */ |
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280 | | - hdmi_cec_pee3 { |
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| 246 | + hdmi-cec-pee3 { |
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281 | 247 | nvidia,pins = "hdmi_cec_pee3"; |
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282 | 248 | nvidia,function = "cec"; |
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283 | 249 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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287 | 253 | }; |
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288 | 254 | |
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289 | 255 | /* Apalis HDMI1_HPD */ |
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290 | | - hdmi_int_pn7 { |
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| 256 | + hdmi-int-pn7 { |
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291 | 257 | nvidia,pins = "hdmi_int_pn7"; |
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292 | 258 | nvidia,function = "rsvd1"; |
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293 | 259 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
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.. | .. |
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297 | 263 | }; |
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298 | 264 | |
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299 | 265 | /* Apalis I2C1 */ |
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300 | | - gen1_i2c_scl_pc4 { |
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| 266 | + gen1-i2c-scl-pc4 { |
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301 | 267 | nvidia,pins = "gen1_i2c_scl_pc4"; |
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302 | 268 | nvidia,function = "i2c1"; |
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303 | 269 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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305 | 271 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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306 | 272 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
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307 | 273 | }; |
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308 | | - gen1_i2c_sda_pc5 { |
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| 274 | + gen1-i2c-sda-pc5 { |
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309 | 275 | nvidia,pins = "gen1_i2c_sda_pc5"; |
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310 | 276 | nvidia,function = "i2c1"; |
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311 | 277 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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315 | 281 | }; |
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316 | 282 | |
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317 | 283 | /* Apalis I2C2 (DDC) */ |
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318 | | - gen2_i2c_scl_pt5 { |
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| 284 | + gen2-i2c-scl-pt5 { |
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319 | 285 | nvidia,pins = "gen2_i2c_scl_pt5"; |
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320 | 286 | nvidia,function = "i2c2"; |
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321 | 287 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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323 | 289 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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324 | 290 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
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325 | 291 | }; |
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326 | | - gen2_i2c_sda_pt6 { |
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| 292 | + gen2-i2c-sda-pt6 { |
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327 | 293 | nvidia,pins = "gen2_i2c_sda_pt6"; |
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328 | 294 | nvidia,function = "i2c2"; |
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329 | 295 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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333 | 299 | }; |
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334 | 300 | |
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335 | 301 | /* Apalis I2C3 (CAM) */ |
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336 | | - cam_i2c_scl_pbb1 { |
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| 302 | + cam-i2c-scl-pbb1 { |
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337 | 303 | nvidia,pins = "cam_i2c_scl_pbb1"; |
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338 | 304 | nvidia,function = "i2c3"; |
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339 | 305 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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341 | 307 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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342 | 308 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
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343 | 309 | }; |
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344 | | - cam_i2c_sda_pbb2 { |
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| 310 | + cam-i2c-sda-pbb2 { |
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345 | 311 | nvidia,pins = "cam_i2c_sda_pbb2"; |
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346 | 312 | nvidia,function = "i2c3"; |
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347 | 313 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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.. | .. |
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351 | 317 | }; |
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352 | 318 | |
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353 | 319 | /* Apalis MMC1 */ |
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354 | | - sdmmc1_cd_n_pv3 { /* CD# GPIO */ |
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| 320 | + sdmmc1-cd-n-pv3 { /* CD# GPIO */ |
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355 | 321 | nvidia,pins = "sdmmc1_wp_n_pv3"; |
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356 | 322 | nvidia,function = "sdmmc1"; |
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357 | 323 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
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358 | 324 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
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359 | 325 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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360 | 326 | }; |
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361 | | - clk2_out_pw5 { /* D5 GPIO */ |
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| 327 | + clk2-out-pw5 { /* D5 GPIO */ |
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362 | 328 | nvidia,pins = "clk2_out_pw5"; |
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363 | 329 | nvidia,function = "rsvd2"; |
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364 | 330 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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365 | 331 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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366 | 332 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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367 | 333 | }; |
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368 | | - sdmmc1_dat3_py4 { |
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| 334 | + sdmmc1-dat3-py4 { |
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369 | 335 | nvidia,pins = "sdmmc1_dat3_py4"; |
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370 | 336 | nvidia,function = "sdmmc1"; |
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371 | 337 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
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372 | 338 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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373 | 339 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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374 | 340 | }; |
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375 | | - sdmmc1_dat2_py5 { |
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| 341 | + sdmmc1-dat2-py5 { |
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376 | 342 | nvidia,pins = "sdmmc1_dat2_py5"; |
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377 | 343 | nvidia,function = "sdmmc1"; |
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378 | 344 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
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379 | 345 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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380 | 346 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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381 | 347 | }; |
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382 | | - sdmmc1_dat1_py6 { |
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| 348 | + sdmmc1-dat1-py6 { |
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383 | 349 | nvidia,pins = "sdmmc1_dat1_py6"; |
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384 | 350 | nvidia,function = "sdmmc1"; |
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385 | 351 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
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386 | 352 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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387 | 353 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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388 | 354 | }; |
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389 | | - sdmmc1_dat0_py7 { |
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| 355 | + sdmmc1-dat0-py7 { |
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390 | 356 | nvidia,pins = "sdmmc1_dat0_py7"; |
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391 | 357 | nvidia,function = "sdmmc1"; |
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392 | 358 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
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393 | 359 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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394 | 360 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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395 | 361 | }; |
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396 | | - sdmmc1_clk_pz0 { |
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| 362 | + sdmmc1-clk-pz0 { |
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397 | 363 | nvidia,pins = "sdmmc1_clk_pz0"; |
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398 | 364 | nvidia,function = "sdmmc1"; |
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399 | 365 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
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400 | 366 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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401 | 367 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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402 | 368 | }; |
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403 | | - sdmmc1_cmd_pz1 { |
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| 369 | + sdmmc1-cmd-pz1 { |
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404 | 370 | nvidia,pins = "sdmmc1_cmd_pz1"; |
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405 | 371 | nvidia,function = "sdmmc1"; |
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406 | 372 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
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407 | 373 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
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408 | 374 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
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409 | 375 | }; |
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410 | | - clk2_req_pcc5 { /* D4 GPIO */ |
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| 376 | + clk2-req-pcc5 { /* D4 GPIO */ |
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411 | 377 | nvidia,pins = "clk2_req_pcc5"; |
---|
412 | 378 | nvidia,function = "rsvd2"; |
---|
413 | 379 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
414 | 380 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
415 | 381 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
416 | 382 | }; |
---|
417 | | - sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */ |
---|
| 383 | + sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ |
---|
418 | 384 | nvidia,pins = "sdmmc3_clk_lb_in_pee5"; |
---|
419 | 385 | nvidia,function = "rsvd2"; |
---|
420 | 386 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
421 | 387 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
422 | 388 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
423 | 389 | }; |
---|
424 | | - usb_vbus_en2_pff1 { /* D7 GPIO */ |
---|
| 390 | + usb-vbus-en2-pff1 { /* D7 GPIO */ |
---|
425 | 391 | nvidia,pins = "usb_vbus_en2_pff1"; |
---|
426 | 392 | nvidia,function = "rsvd2"; |
---|
427 | 393 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
461 | 427 | }; |
---|
462 | 428 | |
---|
463 | 429 | /* Apalis SATA1_ACT# */ |
---|
464 | | - dap1_dout_pn2 { |
---|
| 430 | + dap1-dout-pn2 { |
---|
465 | 431 | nvidia,pins = "dap1_dout_pn2"; |
---|
466 | 432 | nvidia,function = "gmi"; |
---|
467 | 433 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
470 | 436 | }; |
---|
471 | 437 | |
---|
472 | 438 | /* Apalis SD1 */ |
---|
473 | | - sdmmc3_clk_pa6 { |
---|
| 439 | + sdmmc3-clk-pa6 { |
---|
474 | 440 | nvidia,pins = "sdmmc3_clk_pa6"; |
---|
475 | 441 | nvidia,function = "sdmmc3"; |
---|
476 | 442 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
477 | 443 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
478 | 444 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
479 | 445 | }; |
---|
480 | | - sdmmc3_cmd_pa7 { |
---|
| 446 | + sdmmc3-cmd-pa7 { |
---|
481 | 447 | nvidia,pins = "sdmmc3_cmd_pa7"; |
---|
482 | 448 | nvidia,function = "sdmmc3"; |
---|
483 | 449 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
484 | 450 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
485 | 451 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
486 | 452 | }; |
---|
487 | | - sdmmc3_dat3_pb4 { |
---|
| 453 | + sdmmc3-dat3-pb4 { |
---|
488 | 454 | nvidia,pins = "sdmmc3_dat3_pb4"; |
---|
489 | 455 | nvidia,function = "sdmmc3"; |
---|
490 | 456 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
491 | 457 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
492 | 458 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
493 | 459 | }; |
---|
494 | | - sdmmc3_dat2_pb5 { |
---|
| 460 | + sdmmc3-dat2-pb5 { |
---|
495 | 461 | nvidia,pins = "sdmmc3_dat2_pb5"; |
---|
496 | 462 | nvidia,function = "sdmmc3"; |
---|
497 | 463 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
498 | 464 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
499 | 465 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
500 | 466 | }; |
---|
501 | | - sdmmc3_dat1_pb6 { |
---|
| 467 | + sdmmc3-dat1-pb6 { |
---|
502 | 468 | nvidia,pins = "sdmmc3_dat1_pb6"; |
---|
503 | 469 | nvidia,function = "sdmmc3"; |
---|
504 | 470 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
505 | 471 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
506 | 472 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
507 | 473 | }; |
---|
508 | | - sdmmc3_dat0_pb7 { |
---|
| 474 | + sdmmc3-dat0-pb7 { |
---|
509 | 475 | nvidia,pins = "sdmmc3_dat0_pb7"; |
---|
510 | 476 | nvidia,function = "sdmmc3"; |
---|
511 | 477 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
512 | 478 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
513 | 479 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
514 | 480 | }; |
---|
515 | | - sdmmc3_cd_n_pv2 { /* CD# GPIO */ |
---|
| 481 | + sdmmc3-cd-n-pv2 { /* CD# GPIO */ |
---|
516 | 482 | nvidia,pins = "sdmmc3_cd_n_pv2"; |
---|
517 | 483 | nvidia,function = "rsvd3"; |
---|
518 | 484 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
521 | 487 | }; |
---|
522 | 488 | |
---|
523 | 489 | /* Apalis SPDIF */ |
---|
524 | | - spdif_out_pk5 { |
---|
| 490 | + spdif-out-pk5 { |
---|
525 | 491 | nvidia,pins = "spdif_out_pk5"; |
---|
526 | 492 | nvidia,function = "spdif"; |
---|
527 | 493 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
528 | 494 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
529 | 495 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
530 | 496 | }; |
---|
531 | | - spdif_in_pk6 { |
---|
| 497 | + spdif-in-pk6 { |
---|
532 | 498 | nvidia,pins = "spdif_in_pk6"; |
---|
533 | 499 | nvidia,function = "spdif"; |
---|
534 | 500 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
537 | 503 | }; |
---|
538 | 504 | |
---|
539 | 505 | /* Apalis SPI1 */ |
---|
540 | | - ulpi_clk_py0 { |
---|
| 506 | + ulpi-clk-py0 { |
---|
541 | 507 | nvidia,pins = "ulpi_clk_py0"; |
---|
542 | 508 | nvidia,function = "spi1"; |
---|
543 | 509 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
544 | 510 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
545 | 511 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
546 | 512 | }; |
---|
547 | | - ulpi_dir_py1 { |
---|
| 513 | + ulpi-dir-py1 { |
---|
548 | 514 | nvidia,pins = "ulpi_dir_py1"; |
---|
549 | 515 | nvidia,function = "spi1"; |
---|
550 | 516 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
551 | 517 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
552 | 518 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
553 | 519 | }; |
---|
554 | | - ulpi_nxt_py2 { |
---|
| 520 | + ulpi-nxt-py2 { |
---|
555 | 521 | nvidia,pins = "ulpi_nxt_py2"; |
---|
556 | 522 | nvidia,function = "spi1"; |
---|
557 | 523 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
558 | 524 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
559 | 525 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
560 | 526 | }; |
---|
561 | | - ulpi_stp_py3 { |
---|
| 527 | + ulpi-stp-py3 { |
---|
562 | 528 | nvidia,pins = "ulpi_stp_py3"; |
---|
563 | 529 | nvidia,function = "spi1"; |
---|
564 | 530 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
611 | 577 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
612 | 578 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
613 | 579 | }; |
---|
614 | | - uart1_txd_pu0 { |
---|
| 580 | + uart1-txd-pu0 { |
---|
615 | 581 | nvidia,pins = "pu0"; |
---|
616 | 582 | nvidia,function = "uarta"; |
---|
617 | 583 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
618 | 584 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
619 | 585 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
620 | 586 | }; |
---|
621 | | - uart1_rxd_pu1 { |
---|
| 587 | + uart1-rxd-pu1 { |
---|
622 | 588 | nvidia,pins = "pu1"; |
---|
623 | 589 | nvidia,function = "uarta"; |
---|
624 | 590 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
625 | 591 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
626 | 592 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
627 | 593 | }; |
---|
628 | | - uart1_cts_n_pu2 { |
---|
| 594 | + uart1-cts-n-pu2 { |
---|
629 | 595 | nvidia,pins = "pu2"; |
---|
630 | 596 | nvidia,function = "uarta"; |
---|
631 | 597 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
632 | 598 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
633 | 599 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
634 | 600 | }; |
---|
635 | | - uart1_rts_n_pu3 { |
---|
| 601 | + uart1-rts-n-pu3 { |
---|
636 | 602 | nvidia,pins = "pu3"; |
---|
637 | 603 | nvidia,function = "uarta"; |
---|
638 | 604 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
639 | 605 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
640 | 606 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
641 | 607 | }; |
---|
642 | | - uart3_cts_n_pa1 { /* DSR GPIO */ |
---|
| 608 | + uart3-cts-n-pa1 { /* DSR GPIO */ |
---|
643 | 609 | nvidia,pins = "uart3_cts_n_pa1"; |
---|
644 | 610 | nvidia,function = "gmi"; |
---|
645 | 611 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
646 | 612 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
647 | 613 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
648 | 614 | }; |
---|
649 | | - uart3_rts_n_pc0 { /* DTR GPIO */ |
---|
| 615 | + uart3-rts-n-pc0 { /* DTR GPIO */ |
---|
650 | 616 | nvidia,pins = "uart3_rts_n_pc0"; |
---|
651 | 617 | nvidia,function = "gmi"; |
---|
652 | 618 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
655 | 621 | }; |
---|
656 | 622 | |
---|
657 | 623 | /* Apalis UART2 */ |
---|
658 | | - uart2_txd_pc2 { |
---|
| 624 | + uart2-txd-pc2 { |
---|
659 | 625 | nvidia,pins = "uart2_txd_pc2"; |
---|
660 | 626 | nvidia,function = "irda"; |
---|
661 | 627 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
662 | 628 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
663 | 629 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
664 | 630 | }; |
---|
665 | | - uart2_rxd_pc3 { |
---|
| 631 | + uart2-rxd-pc3 { |
---|
666 | 632 | nvidia,pins = "uart2_rxd_pc3"; |
---|
667 | 633 | nvidia,function = "irda"; |
---|
668 | 634 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
669 | 635 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
670 | 636 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
671 | 637 | }; |
---|
672 | | - uart2_cts_n_pj5 { |
---|
| 638 | + uart2-cts-n-pj5 { |
---|
673 | 639 | nvidia,pins = "uart2_cts_n_pj5"; |
---|
674 | 640 | nvidia,function = "uartb"; |
---|
675 | 641 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
676 | 642 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
677 | 643 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
678 | 644 | }; |
---|
679 | | - uart2_rts_n_pj6 { |
---|
| 645 | + uart2-rts-n-pj6 { |
---|
680 | 646 | nvidia,pins = "uart2_rts_n_pj6"; |
---|
681 | 647 | nvidia,function = "uartb"; |
---|
682 | 648 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
685 | 651 | }; |
---|
686 | 652 | |
---|
687 | 653 | /* Apalis UART3 */ |
---|
688 | | - uart3_txd_pw6 { |
---|
| 654 | + uart3-txd-pw6 { |
---|
689 | 655 | nvidia,pins = "uart3_txd_pw6"; |
---|
690 | 656 | nvidia,function = "uartc"; |
---|
691 | 657 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
692 | 658 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
693 | 659 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
694 | 660 | }; |
---|
695 | | - uart3_rxd_pw7 { |
---|
| 661 | + uart3-rxd-pw7 { |
---|
696 | 662 | nvidia,pins = "uart3_rxd_pw7"; |
---|
697 | 663 | nvidia,function = "uartc"; |
---|
698 | 664 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
701 | 667 | }; |
---|
702 | 668 | |
---|
703 | 669 | /* Apalis UART4 */ |
---|
704 | | - uart4_rxd_pb0 { |
---|
| 670 | + uart4-rxd-pb0 { |
---|
705 | 671 | nvidia,pins = "pb0"; |
---|
706 | 672 | nvidia,function = "uartd"; |
---|
707 | 673 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
708 | 674 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
709 | 675 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
710 | 676 | }; |
---|
711 | | - uart4_txd_pj7 { |
---|
| 677 | + uart4-txd-pj7 { |
---|
712 | 678 | nvidia,pins = "pj7"; |
---|
713 | 679 | nvidia,function = "uartd"; |
---|
714 | 680 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
717 | 683 | }; |
---|
718 | 684 | |
---|
719 | 685 | /* Apalis USBH_EN */ |
---|
720 | | - usb_vbus_en1_pn5 { |
---|
| 686 | + usb-vbus-en1-pn5 { |
---|
721 | 687 | nvidia,pins = "usb_vbus_en1_pn5"; |
---|
722 | 688 | nvidia,function = "rsvd2"; |
---|
723 | 689 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
736 | 702 | }; |
---|
737 | 703 | |
---|
738 | 704 | /* Apalis USBO1_EN */ |
---|
739 | | - usb_vbus_en0_pn4 { |
---|
| 705 | + usb-vbus-en0-pn4 { |
---|
740 | 706 | nvidia,pins = "usb_vbus_en0_pn4"; |
---|
741 | 707 | nvidia,function = "rsvd2"; |
---|
742 | 708 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
755 | 721 | }; |
---|
756 | 722 | |
---|
757 | 723 | /* Apalis WAKE1_MICO */ |
---|
758 | | - pex_wake_n_pdd3 { |
---|
| 724 | + pex-wake-n-pdd3 { |
---|
759 | 725 | nvidia,pins = "pex_wake_n_pdd3"; |
---|
760 | 726 | nvidia,function = "rsvd2"; |
---|
761 | 727 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
764 | 730 | }; |
---|
765 | 731 | |
---|
766 | 732 | /* CORE_PWR_REQ */ |
---|
767 | | - core_pwr_req { |
---|
| 733 | + core-pwr-req { |
---|
768 | 734 | nvidia,pins = "core_pwr_req"; |
---|
769 | 735 | nvidia,function = "pwron"; |
---|
770 | 736 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
773 | 739 | }; |
---|
774 | 740 | |
---|
775 | 741 | /* CPU_PWR_REQ */ |
---|
776 | | - cpu_pwr_req { |
---|
| 742 | + cpu-pwr-req { |
---|
777 | 743 | nvidia,pins = "cpu_pwr_req"; |
---|
778 | 744 | nvidia,function = "cpu"; |
---|
779 | 745 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
782 | 748 | }; |
---|
783 | 749 | |
---|
784 | 750 | /* DVFS */ |
---|
785 | | - dvfs_pwm_px0 { |
---|
| 751 | + dvfs-pwm-px0 { |
---|
786 | 752 | nvidia,pins = "dvfs_pwm_px0"; |
---|
787 | 753 | nvidia,function = "cldvfs"; |
---|
788 | 754 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
789 | 755 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
790 | 756 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
791 | 757 | }; |
---|
792 | | - dvfs_clk_px2 { |
---|
| 758 | + dvfs-clk-px2 { |
---|
793 | 759 | nvidia,pins = "dvfs_clk_px2"; |
---|
794 | 760 | nvidia,function = "cldvfs"; |
---|
795 | 761 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
798 | 764 | }; |
---|
799 | 765 | |
---|
800 | 766 | /* eMMC */ |
---|
801 | | - sdmmc4_dat0_paa0 { |
---|
| 767 | + sdmmc4-dat0-paa0 { |
---|
802 | 768 | nvidia,pins = "sdmmc4_dat0_paa0"; |
---|
803 | 769 | nvidia,function = "sdmmc4"; |
---|
804 | 770 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
805 | 771 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
806 | 772 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
807 | 773 | }; |
---|
808 | | - sdmmc4_dat1_paa1 { |
---|
| 774 | + sdmmc4-dat1-paa1 { |
---|
809 | 775 | nvidia,pins = "sdmmc4_dat1_paa1"; |
---|
810 | 776 | nvidia,function = "sdmmc4"; |
---|
811 | 777 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
812 | 778 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
813 | 779 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
814 | 780 | }; |
---|
815 | | - sdmmc4_dat2_paa2 { |
---|
| 781 | + sdmmc4-dat2-paa2 { |
---|
816 | 782 | nvidia,pins = "sdmmc4_dat2_paa2"; |
---|
817 | 783 | nvidia,function = "sdmmc4"; |
---|
818 | 784 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
819 | 785 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
820 | 786 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
821 | 787 | }; |
---|
822 | | - sdmmc4_dat3_paa3 { |
---|
| 788 | + sdmmc4-dat3-paa3 { |
---|
823 | 789 | nvidia,pins = "sdmmc4_dat3_paa3"; |
---|
824 | 790 | nvidia,function = "sdmmc4"; |
---|
825 | 791 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
826 | 792 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
827 | 793 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
828 | 794 | }; |
---|
829 | | - sdmmc4_dat4_paa4 { |
---|
| 795 | + sdmmc4-dat4-paa4 { |
---|
830 | 796 | nvidia,pins = "sdmmc4_dat4_paa4"; |
---|
831 | 797 | nvidia,function = "sdmmc4"; |
---|
832 | 798 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
833 | 799 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
834 | 800 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
835 | 801 | }; |
---|
836 | | - sdmmc4_dat5_paa5 { |
---|
| 802 | + sdmmc4-dat5-paa5 { |
---|
837 | 803 | nvidia,pins = "sdmmc4_dat5_paa5"; |
---|
838 | 804 | nvidia,function = "sdmmc4"; |
---|
839 | 805 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
840 | 806 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
841 | 807 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
842 | 808 | }; |
---|
843 | | - sdmmc4_dat6_paa6 { |
---|
| 809 | + sdmmc4-dat6-paa6 { |
---|
844 | 810 | nvidia,pins = "sdmmc4_dat6_paa6"; |
---|
845 | 811 | nvidia,function = "sdmmc4"; |
---|
846 | 812 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
847 | 813 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
848 | 814 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
849 | 815 | }; |
---|
850 | | - sdmmc4_dat7_paa7 { |
---|
| 816 | + sdmmc4-dat7-paa7 { |
---|
851 | 817 | nvidia,pins = "sdmmc4_dat7_paa7"; |
---|
852 | 818 | nvidia,function = "sdmmc4"; |
---|
853 | 819 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
854 | 820 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
855 | 821 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
856 | 822 | }; |
---|
857 | | - sdmmc4_clk_pcc4 { |
---|
| 823 | + sdmmc4-clk-pcc4 { |
---|
858 | 824 | nvidia,pins = "sdmmc4_clk_pcc4"; |
---|
859 | 825 | nvidia,function = "sdmmc4"; |
---|
860 | 826 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
861 | 827 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
862 | 828 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
863 | 829 | }; |
---|
864 | | - sdmmc4_cmd_pt7 { |
---|
| 830 | + sdmmc4-cmd-pt7 { |
---|
865 | 831 | nvidia,pins = "sdmmc4_cmd_pt7"; |
---|
866 | 832 | nvidia,function = "sdmmc4"; |
---|
867 | 833 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
870 | 836 | }; |
---|
871 | 837 | |
---|
872 | 838 | /* JTAG_RTCK */ |
---|
873 | | - jtag_rtck { |
---|
| 839 | + jtag-rtck { |
---|
874 | 840 | nvidia,pins = "jtag_rtck"; |
---|
875 | 841 | nvidia,function = "rtck"; |
---|
876 | 842 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
879 | 845 | }; |
---|
880 | 846 | |
---|
881 | 847 | /* LAN_DEV_OFF# */ |
---|
882 | | - ulpi_data5_po6 { |
---|
| 848 | + ulpi-data5-po6 { |
---|
883 | 849 | nvidia,pins = "ulpi_data5_po6"; |
---|
884 | 850 | nvidia,function = "ulpi"; |
---|
885 | 851 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
888 | 854 | }; |
---|
889 | 855 | |
---|
890 | 856 | /* LAN_RESET# */ |
---|
891 | | - kb_row10_ps2 { |
---|
| 857 | + kb-row10-ps2 { |
---|
892 | 858 | nvidia,pins = "kb_row10_ps2"; |
---|
893 | 859 | nvidia,function = "rsvd2"; |
---|
894 | 860 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
897 | 863 | }; |
---|
898 | 864 | |
---|
899 | 865 | /* LAN_WAKE# */ |
---|
900 | | - ulpi_data4_po5 { |
---|
| 866 | + ulpi-data4-po5 { |
---|
901 | 867 | nvidia,pins = "ulpi_data4_po5"; |
---|
902 | 868 | nvidia,function = "ulpi"; |
---|
903 | 869 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
951 | 917 | }; |
---|
952 | 918 | |
---|
953 | 919 | /* MCU SPI */ |
---|
954 | | - gpio_x4_aud_px4 { |
---|
| 920 | + gpio-x4-aud-px4 { |
---|
955 | 921 | nvidia,pins = "gpio_x4_aud_px4"; |
---|
956 | 922 | nvidia,function = "spi2"; |
---|
957 | 923 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
958 | 924 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
959 | 925 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
960 | 926 | }; |
---|
961 | | - gpio_x5_aud_px5 { |
---|
| 927 | + gpio-x5-aud-px5 { |
---|
962 | 928 | nvidia,pins = "gpio_x5_aud_px5"; |
---|
963 | 929 | nvidia,function = "spi2"; |
---|
964 | 930 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
965 | 931 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
966 | 932 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
967 | 933 | }; |
---|
968 | | - gpio_x6_aud_px6 { /* MCU_CS */ |
---|
| 934 | + gpio-x6-aud-px6 { /* MCU_CS */ |
---|
969 | 935 | nvidia,pins = "gpio_x6_aud_px6"; |
---|
970 | 936 | nvidia,function = "spi2"; |
---|
971 | 937 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
972 | 938 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
---|
973 | 939 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
974 | 940 | }; |
---|
975 | | - gpio_x7_aud_px7 { |
---|
| 941 | + gpio-x7-aud-px7 { |
---|
976 | 942 | nvidia,pins = "gpio_x7_aud_px7"; |
---|
977 | 943 | nvidia,function = "spi2"; |
---|
978 | 944 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
979 | 945 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
980 | 946 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
981 | 947 | }; |
---|
982 | | - gpio_w2_aud_pw2 { /* MCU_CSEZP */ |
---|
| 948 | + gpio-w2-aud-pw2 { /* MCU_CSEZP */ |
---|
983 | 949 | nvidia,pins = "gpio_w2_aud_pw2"; |
---|
984 | 950 | nvidia,function = "spi2"; |
---|
985 | 951 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
988 | 954 | }; |
---|
989 | 955 | |
---|
990 | 956 | /* PMIC_CLK_32K */ |
---|
991 | | - clk_32k_in { |
---|
| 957 | + clk-32k-in { |
---|
992 | 958 | nvidia,pins = "clk_32k_in"; |
---|
993 | 959 | nvidia,function = "clk"; |
---|
994 | 960 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
997 | 963 | }; |
---|
998 | 964 | |
---|
999 | 965 | /* PMIC_CPU_OC_INT */ |
---|
1000 | | - clk_32k_out_pa0 { |
---|
| 966 | + clk-32k-out-pa0 { |
---|
1001 | 967 | nvidia,pins = "clk_32k_out_pa0"; |
---|
1002 | 968 | nvidia,function = "soc"; |
---|
1003 | 969 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
1006 | 972 | }; |
---|
1007 | 973 | |
---|
1008 | 974 | /* PWR_I2C */ |
---|
1009 | | - pwr_i2c_scl_pz6 { |
---|
| 975 | + pwr-i2c-scl-pz6 { |
---|
1010 | 976 | nvidia,pins = "pwr_i2c_scl_pz6"; |
---|
1011 | 977 | nvidia,function = "i2cpwr"; |
---|
1012 | 978 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
1014 | 980 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
---|
1015 | 981 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
---|
1016 | 982 | }; |
---|
1017 | | - pwr_i2c_sda_pz7 { |
---|
| 983 | + pwr-i2c-sda-pz7 { |
---|
1018 | 984 | nvidia,pins = "pwr_i2c_sda_pz7"; |
---|
1019 | 985 | nvidia,function = "i2cpwr"; |
---|
1020 | 986 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
1024 | 990 | }; |
---|
1025 | 991 | |
---|
1026 | 992 | /* PWR_INT_N */ |
---|
1027 | | - pwr_int_n { |
---|
| 993 | + pwr-int-n { |
---|
1028 | 994 | nvidia,pins = "pwr_int_n"; |
---|
1029 | 995 | nvidia,function = "pmi"; |
---|
1030 | 996 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
1042 | 1008 | }; |
---|
1043 | 1009 | |
---|
1044 | 1010 | /* RESET_OUT_N */ |
---|
1045 | | - reset_out_n { |
---|
| 1011 | + reset-out-n { |
---|
1046 | 1012 | nvidia,pins = "reset_out_n"; |
---|
1047 | 1013 | nvidia,function = "reset_out_n"; |
---|
1048 | 1014 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
1051 | 1017 | }; |
---|
1052 | 1018 | |
---|
1053 | 1019 | /* SHIFT_CTRL_DIR_IN */ |
---|
1054 | | - kb_row0_pr0 { |
---|
| 1020 | + kb-row0-pr0 { |
---|
1055 | 1021 | nvidia,pins = "kb_row0_pr0"; |
---|
1056 | 1022 | nvidia,function = "rsvd2"; |
---|
1057 | 1023 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1058 | 1024 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1059 | 1025 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1060 | 1026 | }; |
---|
1061 | | - kb_row1_pr1 { |
---|
| 1027 | + kb-row1-pr1 { |
---|
1062 | 1028 | nvidia,pins = "kb_row1_pr1"; |
---|
1063 | 1029 | nvidia,function = "rsvd2"; |
---|
1064 | 1030 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
.. | .. |
---|
1067 | 1033 | }; |
---|
1068 | 1034 | |
---|
1069 | 1035 | /* Configure level-shifter as output for HDA */ |
---|
1070 | | - kb_row11_ps3 { |
---|
| 1036 | + kb-row11-ps3 { |
---|
1071 | 1037 | nvidia,pins = "kb_row11_ps3"; |
---|
1072 | 1038 | nvidia,function = "rsvd2"; |
---|
1073 | 1039 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
1076 | 1042 | }; |
---|
1077 | 1043 | |
---|
1078 | 1044 | /* SHIFT_CTRL_DIR_OUT */ |
---|
1079 | | - kb_col5_pq5 { |
---|
| 1045 | + kb-col5-pq5 { |
---|
1080 | 1046 | nvidia,pins = "kb_col5_pq5"; |
---|
1081 | 1047 | nvidia,function = "rsvd2"; |
---|
1082 | 1048 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
1083 | 1049 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1084 | 1050 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1085 | 1051 | }; |
---|
1086 | | - kb_col6_pq6 { |
---|
| 1052 | + kb-col6-pq6 { |
---|
1087 | 1053 | nvidia,pins = "kb_col6_pq6"; |
---|
1088 | 1054 | nvidia,function = "rsvd2"; |
---|
1089 | 1055 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
1090 | 1056 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1091 | 1057 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1092 | 1058 | }; |
---|
1093 | | - kb_col7_pq7 { |
---|
| 1059 | + kb-col7-pq7 { |
---|
1094 | 1060 | nvidia,pins = "kb_col7_pq7"; |
---|
1095 | 1061 | nvidia,function = "rsvd2"; |
---|
1096 | 1062 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
---|
.. | .. |
---|
1099 | 1065 | }; |
---|
1100 | 1066 | |
---|
1101 | 1067 | /* SHIFT_CTRL_OE */ |
---|
1102 | | - kb_col0_pq0 { |
---|
| 1068 | + kb-col0-pq0 { |
---|
1103 | 1069 | nvidia,pins = "kb_col0_pq0"; |
---|
1104 | 1070 | nvidia,function = "rsvd2"; |
---|
1105 | 1071 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1106 | 1072 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1107 | 1073 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1108 | 1074 | }; |
---|
1109 | | - kb_col1_pq1 { |
---|
| 1075 | + kb-col1-pq1 { |
---|
1110 | 1076 | nvidia,pins = "kb_col1_pq1"; |
---|
1111 | 1077 | nvidia,function = "rsvd2"; |
---|
1112 | 1078 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1113 | 1079 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1114 | 1080 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1115 | 1081 | }; |
---|
1116 | | - kb_col2_pq2 { |
---|
| 1082 | + kb-col2-pq2 { |
---|
1117 | 1083 | nvidia,pins = "kb_col2_pq2"; |
---|
1118 | 1084 | nvidia,function = "rsvd2"; |
---|
1119 | 1085 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1120 | 1086 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1121 | 1087 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1122 | 1088 | }; |
---|
1123 | | - kb_col4_pq4 { |
---|
| 1089 | + kb-col4-pq4 { |
---|
1124 | 1090 | nvidia,pins = "kb_col4_pq4"; |
---|
1125 | 1091 | nvidia,function = "kbc"; |
---|
1126 | 1092 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1127 | 1093 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1128 | 1094 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1129 | 1095 | }; |
---|
1130 | | - kb_row2_pr2 { |
---|
| 1096 | + kb-row2-pr2 { |
---|
1131 | 1097 | nvidia,pins = "kb_row2_pr2"; |
---|
1132 | 1098 | nvidia,function = "rsvd2"; |
---|
1133 | 1099 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
.. | .. |
---|
1145 | 1111 | }; |
---|
1146 | 1112 | |
---|
1147 | 1113 | /* TOUCH_INT */ |
---|
1148 | | - gpio_w3_aud_pw3 { |
---|
| 1114 | + gpio-w3-aud-pw3 { |
---|
1149 | 1115 | nvidia,pins = "gpio_w3_aud_pw3"; |
---|
1150 | 1116 | nvidia,function = "spi6"; |
---|
1151 | 1117 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
1286 | 1252 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1287 | 1253 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1288 | 1254 | }; |
---|
1289 | | - dap1_fs_pn0 { /* NC */ |
---|
| 1255 | + dap1-fs-pn0 { /* NC */ |
---|
1290 | 1256 | nvidia,pins = "dap1_fs_pn0"; |
---|
1291 | 1257 | nvidia,function = "rsvd4"; |
---|
1292 | 1258 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1293 | 1259 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1294 | 1260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1295 | 1261 | }; |
---|
1296 | | - dap1_din_pn1 { /* NC */ |
---|
| 1262 | + dap1-din-pn1 { /* NC */ |
---|
1297 | 1263 | nvidia,pins = "dap1_din_pn1"; |
---|
1298 | 1264 | nvidia,function = "rsvd4"; |
---|
1299 | 1265 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1300 | 1266 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1301 | 1267 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1302 | 1268 | }; |
---|
1303 | | - dap1_sclk_pn3 { /* NC */ |
---|
| 1269 | + dap1-sclk-pn3 { /* NC */ |
---|
1304 | 1270 | nvidia,pins = "dap1_sclk_pn3"; |
---|
1305 | 1271 | nvidia,function = "rsvd4"; |
---|
1306 | 1272 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1307 | 1273 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1308 | 1274 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1309 | 1275 | }; |
---|
1310 | | - ulpi_data7_po0 { /* NC */ |
---|
| 1276 | + ulpi-data7-po0 { /* NC */ |
---|
1311 | 1277 | nvidia,pins = "ulpi_data7_po0"; |
---|
1312 | 1278 | nvidia,function = "ulpi"; |
---|
1313 | 1279 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1314 | 1280 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1315 | 1281 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1316 | 1282 | }; |
---|
1317 | | - ulpi_data0_po1 { /* NC */ |
---|
| 1283 | + ulpi-data0-po1 { /* NC */ |
---|
1318 | 1284 | nvidia,pins = "ulpi_data0_po1"; |
---|
1319 | 1285 | nvidia,function = "ulpi"; |
---|
1320 | 1286 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1321 | 1287 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1322 | 1288 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1323 | 1289 | }; |
---|
1324 | | - ulpi_data1_po2 { /* NC */ |
---|
| 1290 | + ulpi-data1-po2 { /* NC */ |
---|
1325 | 1291 | nvidia,pins = "ulpi_data1_po2"; |
---|
1326 | 1292 | nvidia,function = "ulpi"; |
---|
1327 | 1293 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1328 | 1294 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1329 | 1295 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1330 | 1296 | }; |
---|
1331 | | - ulpi_data2_po3 { /* NC */ |
---|
| 1297 | + ulpi-data2-po3 { /* NC */ |
---|
1332 | 1298 | nvidia,pins = "ulpi_data2_po3"; |
---|
1333 | 1299 | nvidia,function = "ulpi"; |
---|
1334 | 1300 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1335 | 1301 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1336 | 1302 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1337 | 1303 | }; |
---|
1338 | | - ulpi_data3_po4 { /* NC */ |
---|
| 1304 | + ulpi-data3-po4 { /* NC */ |
---|
1339 | 1305 | nvidia,pins = "ulpi_data3_po4"; |
---|
1340 | 1306 | nvidia,function = "ulpi"; |
---|
1341 | 1307 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1342 | 1308 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1343 | 1309 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1344 | 1310 | }; |
---|
1345 | | - ulpi_data6_po7 { /* NC */ |
---|
| 1311 | + ulpi-data6-po7 { /* NC */ |
---|
1346 | 1312 | nvidia,pins = "ulpi_data6_po7"; |
---|
1347 | 1313 | nvidia,function = "ulpi"; |
---|
1348 | 1314 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1349 | 1315 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1350 | 1316 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1351 | 1317 | }; |
---|
1352 | | - dap4_fs_pp4 { /* NC */ |
---|
| 1318 | + dap4-fs-pp4 { /* NC */ |
---|
1353 | 1319 | nvidia,pins = "dap4_fs_pp4"; |
---|
1354 | 1320 | nvidia,function = "rsvd4"; |
---|
1355 | 1321 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1356 | 1322 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1357 | 1323 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1358 | 1324 | }; |
---|
1359 | | - dap4_din_pp5 { /* NC */ |
---|
| 1325 | + dap4-din-pp5 { /* NC */ |
---|
1360 | 1326 | nvidia,pins = "dap4_din_pp5"; |
---|
1361 | 1327 | nvidia,function = "rsvd3"; |
---|
1362 | 1328 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1363 | 1329 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1364 | 1330 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1365 | 1331 | }; |
---|
1366 | | - dap4_dout_pp6 { /* NC */ |
---|
| 1332 | + dap4-dout-pp6 { /* NC */ |
---|
1367 | 1333 | nvidia,pins = "dap4_dout_pp6"; |
---|
1368 | 1334 | nvidia,function = "rsvd4"; |
---|
1369 | 1335 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1370 | 1336 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1371 | 1337 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1372 | 1338 | }; |
---|
1373 | | - dap4_sclk_pp7 { /* NC */ |
---|
| 1339 | + dap4-sclk-pp7 { /* NC */ |
---|
1374 | 1340 | nvidia,pins = "dap4_sclk_pp7"; |
---|
1375 | 1341 | nvidia,function = "rsvd3"; |
---|
1376 | 1342 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1377 | 1343 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1378 | 1344 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1379 | 1345 | }; |
---|
1380 | | - kb_col3_pq3 { /* NC */ |
---|
| 1346 | + kb-col3-pq3 { /* NC */ |
---|
1381 | 1347 | nvidia,pins = "kb_col3_pq3"; |
---|
1382 | 1348 | nvidia,function = "kbc"; |
---|
1383 | 1349 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1384 | 1350 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1385 | 1351 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1386 | 1352 | }; |
---|
1387 | | - kb_row3_pr3 { /* NC */ |
---|
| 1353 | + kb-row3-pr3 { /* NC */ |
---|
1388 | 1354 | nvidia,pins = "kb_row3_pr3"; |
---|
1389 | 1355 | nvidia,function = "kbc"; |
---|
1390 | 1356 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1391 | 1357 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1392 | 1358 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1393 | 1359 | }; |
---|
1394 | | - kb_row4_pr4 { /* NC */ |
---|
| 1360 | + kb-row4-pr4 { /* NC */ |
---|
1395 | 1361 | nvidia,pins = "kb_row4_pr4"; |
---|
1396 | 1362 | nvidia,function = "rsvd3"; |
---|
1397 | 1363 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1398 | 1364 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1399 | 1365 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1400 | 1366 | }; |
---|
1401 | | - kb_row5_pr5 { /* NC */ |
---|
| 1367 | + kb-row5-pr5 { /* NC */ |
---|
1402 | 1368 | nvidia,pins = "kb_row5_pr5"; |
---|
1403 | 1369 | nvidia,function = "rsvd3"; |
---|
1404 | 1370 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1405 | 1371 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1406 | 1372 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1407 | 1373 | }; |
---|
1408 | | - kb_row6_pr6 { /* NC */ |
---|
| 1374 | + kb-row6-pr6 { /* NC */ |
---|
1409 | 1375 | nvidia,pins = "kb_row6_pr6"; |
---|
1410 | 1376 | nvidia,function = "kbc"; |
---|
1411 | 1377 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1412 | 1378 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1413 | 1379 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1414 | 1380 | }; |
---|
1415 | | - kb_row7_pr7 { /* NC */ |
---|
| 1381 | + kb-row7-pr7 { /* NC */ |
---|
1416 | 1382 | nvidia,pins = "kb_row7_pr7"; |
---|
1417 | 1383 | nvidia,function = "rsvd2"; |
---|
1418 | 1384 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1419 | 1385 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1420 | 1386 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1421 | 1387 | }; |
---|
1422 | | - kb_row8_ps0 { /* NC */ |
---|
| 1388 | + kb-row8-ps0 { /* NC */ |
---|
1423 | 1389 | nvidia,pins = "kb_row8_ps0"; |
---|
1424 | 1390 | nvidia,function = "rsvd2"; |
---|
1425 | 1391 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1426 | 1392 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1427 | 1393 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1428 | 1394 | }; |
---|
1429 | | - kb_row9_ps1 { /* NC */ |
---|
| 1395 | + kb-row9-ps1 { /* NC */ |
---|
1430 | 1396 | nvidia,pins = "kb_row9_ps1"; |
---|
1431 | 1397 | nvidia,function = "rsvd2"; |
---|
1432 | 1398 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1433 | 1399 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1434 | 1400 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1435 | 1401 | }; |
---|
1436 | | - kb_row12_ps4 { /* NC */ |
---|
| 1402 | + kb-row12-ps4 { /* NC */ |
---|
1437 | 1403 | nvidia,pins = "kb_row12_ps4"; |
---|
1438 | 1404 | nvidia,function = "rsvd2"; |
---|
1439 | 1405 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1440 | 1406 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1441 | 1407 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1442 | 1408 | }; |
---|
1443 | | - kb_row13_ps5 { /* NC */ |
---|
| 1409 | + kb-row13-ps5 { /* NC */ |
---|
1444 | 1410 | nvidia,pins = "kb_row13_ps5"; |
---|
1445 | 1411 | nvidia,function = "rsvd2"; |
---|
1446 | 1412 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1447 | 1413 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1448 | 1414 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1449 | 1415 | }; |
---|
1450 | | - kb_row14_ps6 { /* NC */ |
---|
| 1416 | + kb-row14-ps6 { /* NC */ |
---|
1451 | 1417 | nvidia,pins = "kb_row14_ps6"; |
---|
1452 | 1418 | nvidia,function = "rsvd2"; |
---|
1453 | 1419 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1454 | 1420 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1455 | 1421 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1456 | 1422 | }; |
---|
1457 | | - kb_row15_ps7 { /* NC */ |
---|
| 1423 | + kb-row15-ps7 { /* NC */ |
---|
1458 | 1424 | nvidia,pins = "kb_row15_ps7"; |
---|
1459 | 1425 | nvidia,function = "rsvd3"; |
---|
1460 | 1426 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1461 | 1427 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1462 | 1428 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1463 | 1429 | }; |
---|
1464 | | - kb_row16_pt0 { /* NC */ |
---|
| 1430 | + kb-row16-pt0 { /* NC */ |
---|
1465 | 1431 | nvidia,pins = "kb_row16_pt0"; |
---|
1466 | 1432 | nvidia,function = "rsvd2"; |
---|
1467 | 1433 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1468 | 1434 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1469 | 1435 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1470 | 1436 | }; |
---|
1471 | | - kb_row17_pt1 { /* NC */ |
---|
| 1437 | + kb-row17-pt1 { /* NC */ |
---|
1472 | 1438 | nvidia,pins = "kb_row17_pt1"; |
---|
1473 | 1439 | nvidia,function = "rsvd2"; |
---|
1474 | 1440 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
.. | .. |
---|
1496 | 1462 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1497 | 1463 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1498 | 1464 | }; |
---|
1499 | | - gpio_x1_aud_px1 { /* NC */ |
---|
| 1465 | + gpio-x1-aud-px1 { /* NC */ |
---|
1500 | 1466 | nvidia,pins = "gpio_x1_aud_px1"; |
---|
1501 | 1467 | nvidia,function = "rsvd2"; |
---|
1502 | 1468 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1503 | 1469 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1504 | 1470 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1505 | 1471 | }; |
---|
1506 | | - gpio_x3_aud_px3 { /* NC */ |
---|
| 1472 | + gpio-x3-aud-px3 { /* NC */ |
---|
1507 | 1473 | nvidia,pins = "gpio_x3_aud_px3"; |
---|
1508 | 1474 | nvidia,function = "rsvd4"; |
---|
1509 | 1475 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
.. | .. |
---|
1531 | 1497 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1532 | 1498 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1533 | 1499 | }; |
---|
1534 | | - clk3_req_pee1 { /* NC */ |
---|
| 1500 | + clk3-req-pee1 { /* NC */ |
---|
1535 | 1501 | nvidia,pins = "clk3_req_pee1"; |
---|
1536 | 1502 | nvidia,function = "rsvd2"; |
---|
1537 | 1503 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
1538 | 1504 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
---|
1539 | 1505 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
---|
1540 | 1506 | }; |
---|
1541 | | - dap_mclk1_req_pee2 { /* NC */ |
---|
| 1507 | + dap-mclk1-req-pee2 { /* NC */ |
---|
1542 | 1508 | nvidia,pins = "dap_mclk1_req_pee2"; |
---|
1543 | 1509 | nvidia,function = "rsvd4"; |
---|
1544 | 1510 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
---|
.. | .. |
---|
1554 | 1520 | * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 |
---|
1555 | 1521 | * bits being set to 0xfffd according to the TRM! |
---|
1556 | 1522 | */ |
---|
1557 | | - sdmmc3_clk_lb_out_pee4 { /* NC */ |
---|
| 1523 | + sdmmc3-clk-lb-out-pee4 { /* NC */ |
---|
1558 | 1524 | nvidia,pins = "sdmmc3_clk_lb_out_pee4"; |
---|
1559 | 1525 | nvidia,function = "sdmmc3"; |
---|
1560 | 1526 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
---|
.. | .. |
---|
1589 | 1555 | sgtl5000: codec@a { |
---|
1590 | 1556 | compatible = "fsl,sgtl5000"; |
---|
1591 | 1557 | reg = <0x0a>; |
---|
1592 | | - VDDA-supply = <®_3v3>; |
---|
1593 | | - VDDIO-supply = <&vddio_1v8>; |
---|
| 1558 | + #sound-dai-cells = <0>; |
---|
| 1559 | + VDDA-supply = <®_module_3v3_audio>; |
---|
| 1560 | + VDDD-supply = <®_1v8_vddio>; |
---|
| 1561 | + VDDIO-supply = <®_1v8_vddio>; |
---|
1594 | 1562 | clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; |
---|
1595 | 1563 | }; |
---|
1596 | 1564 | |
---|
.. | .. |
---|
1607 | 1575 | pinctrl-0 = <&as3722_default>; |
---|
1608 | 1576 | |
---|
1609 | 1577 | as3722_default: pinmux { |
---|
1610 | | - gpio2_7 { |
---|
| 1578 | + gpio2-7 { |
---|
1611 | 1579 | pins = "gpio2", /* PWR_EN_+V3.3 */ |
---|
1612 | 1580 | "gpio7"; /* +V1.6_LPO */ |
---|
1613 | 1581 | function = "gpio"; |
---|
1614 | 1582 | bias-pull-up; |
---|
1615 | 1583 | }; |
---|
1616 | 1584 | |
---|
1617 | | - gpio0_1_3_4_5_6 { |
---|
| 1585 | + gpio0-1-3-4-5-6 { |
---|
1618 | 1586 | pins = "gpio0", "gpio1", "gpio3", |
---|
1619 | 1587 | "gpio4", "gpio5", "gpio6"; |
---|
1620 | 1588 | bias-high-impedance; |
---|
.. | .. |
---|
1622 | 1590 | }; |
---|
1623 | 1591 | |
---|
1624 | 1592 | regulators { |
---|
1625 | | - vsup-sd2-supply = <®_3v3>; |
---|
1626 | | - vsup-sd3-supply = <®_3v3>; |
---|
1627 | | - vsup-sd4-supply = <®_3v3>; |
---|
1628 | | - vsup-sd5-supply = <®_3v3>; |
---|
1629 | | - vin-ldo0-supply = <&vddio_ddr_1v35>; |
---|
1630 | | - vin-ldo1-6-supply = <®_3v3>; |
---|
1631 | | - vin-ldo2-5-7-supply = <&vddio_1v8>; |
---|
1632 | | - vin-ldo3-4-supply = <®_3v3>; |
---|
1633 | | - vin-ldo9-10-supply = <®_3v3>; |
---|
1634 | | - vin-ldo11-supply = <®_3v3>; |
---|
| 1593 | + vsup-sd2-supply = <®_module_3v3>; |
---|
| 1594 | + vsup-sd3-supply = <®_module_3v3>; |
---|
| 1595 | + vsup-sd4-supply = <®_module_3v3>; |
---|
| 1596 | + vsup-sd5-supply = <®_module_3v3>; |
---|
| 1597 | + vin-ldo0-supply = <®_1v35_vddio_ddr>; |
---|
| 1598 | + vin-ldo1-6-supply = <®_module_3v3>; |
---|
| 1599 | + vin-ldo2-5-7-supply = <®_1v8_vddio>; |
---|
| 1600 | + vin-ldo3-4-supply = <®_module_3v3>; |
---|
| 1601 | + vin-ldo9-10-supply = <®_module_3v3>; |
---|
| 1602 | + vin-ldo11-supply = <®_module_3v3>; |
---|
1635 | 1603 | |
---|
1636 | | - vdd_cpu: sd0 { |
---|
| 1604 | + reg_vdd_cpu: sd0 { |
---|
1637 | 1605 | regulator-name = "+VDD_CPU_AP"; |
---|
1638 | 1606 | regulator-min-microvolt = <700000>; |
---|
1639 | 1607 | regulator-max-microvolt = <1400000>; |
---|
.. | .. |
---|
1655 | 1623 | ams,ext-control = <1>; |
---|
1656 | 1624 | }; |
---|
1657 | 1625 | |
---|
1658 | | - vddio_ddr_1v35: sd2 { |
---|
| 1626 | + reg_1v35_vddio_ddr: sd2 { |
---|
1659 | 1627 | regulator-name = |
---|
1660 | 1628 | "+V1.35_VDDIO_DDR(sd2)"; |
---|
1661 | 1629 | regulator-min-microvolt = <1350000>; |
---|
.. | .. |
---|
1673 | 1641 | regulator-boot-on; |
---|
1674 | 1642 | }; |
---|
1675 | 1643 | |
---|
1676 | | - vdd_1v05: sd4 { |
---|
| 1644 | + reg_1v05_vdd: sd4 { |
---|
1677 | 1645 | regulator-name = "+V1.05"; |
---|
1678 | 1646 | regulator-min-microvolt = <1050000>; |
---|
1679 | 1647 | regulator-max-microvolt = <1050000>; |
---|
1680 | 1648 | }; |
---|
1681 | 1649 | |
---|
1682 | | - vddio_1v8: sd5 { |
---|
| 1650 | + reg_1v8_vddio: sd5 { |
---|
1683 | 1651 | regulator-name = "+V1.8"; |
---|
1684 | 1652 | regulator-min-microvolt = <1800000>; |
---|
1685 | 1653 | regulator-max-microvolt = <1800000>; |
---|
.. | .. |
---|
1687 | 1655 | regulator-always-on; |
---|
1688 | 1656 | }; |
---|
1689 | 1657 | |
---|
1690 | | - vdd_gpu: sd6 { |
---|
| 1658 | + reg_vdd_gpu: sd6 { |
---|
1691 | 1659 | regulator-name = "+VDD_GPU_AP"; |
---|
1692 | 1660 | regulator-min-microvolt = <650000>; |
---|
1693 | 1661 | regulator-max-microvolt = <1200000>; |
---|
.. | .. |
---|
1697 | 1665 | regulator-always-on; |
---|
1698 | 1666 | }; |
---|
1699 | 1667 | |
---|
1700 | | - avdd_1v05: ldo0 { |
---|
| 1668 | + reg_1v05_avdd: ldo0 { |
---|
1701 | 1669 | regulator-name = "+V1.05_AVDD"; |
---|
1702 | 1670 | regulator-min-microvolt = <1050000>; |
---|
1703 | 1671 | regulator-max-microvolt = <1050000>; |
---|
.. | .. |
---|
1772 | 1740 | * TMP451 temperature sensor |
---|
1773 | 1741 | * Note: THERM_N directly connected to AS3722 PMIC THERM |
---|
1774 | 1742 | */ |
---|
1775 | | - temperature-sensor@4c { |
---|
| 1743 | + temp-sensor@4c { |
---|
1776 | 1744 | compatible = "ti,tmp451"; |
---|
1777 | 1745 | reg = <0x4c>; |
---|
1778 | 1746 | interrupt-parent = <&gpio>; |
---|
1779 | 1747 | interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; |
---|
1780 | 1748 | #thermal-sensor-cells = <1>; |
---|
| 1749 | + vcc-supply = <®_module_3v3>; |
---|
1781 | 1750 | }; |
---|
1782 | 1751 | }; |
---|
1783 | 1752 | |
---|
.. | .. |
---|
1809 | 1778 | sata@70020000 { |
---|
1810 | 1779 | phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; |
---|
1811 | 1780 | phy-names = "sata-0"; |
---|
1812 | | - avdd-supply = <&vdd_1v05>; |
---|
1813 | | - hvdd-supply = <®_3v3>; |
---|
1814 | | - vddio-supply = <&vdd_1v05>; |
---|
| 1781 | + avdd-supply = <®_1v05_vdd>; |
---|
| 1782 | + hvdd-supply = <®_module_3v3>; |
---|
| 1783 | + vddio-supply = <®_1v05_vdd>; |
---|
1815 | 1784 | }; |
---|
1816 | 1785 | |
---|
1817 | 1786 | usb@70090000 { |
---|
.. | .. |
---|
1822 | 1791 | <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, |
---|
1823 | 1792 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; |
---|
1824 | 1793 | phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; |
---|
1825 | | - avddio-pex-supply = <&vdd_1v05>; |
---|
1826 | | - avdd-pll-erefe-supply = <&avdd_1v05>; |
---|
1827 | | - avdd-pll-utmip-supply = <&vddio_1v8>; |
---|
1828 | | - avdd-usb-ss-pll-supply = <&vdd_1v05>; |
---|
1829 | | - avdd-usb-supply = <®_3v3>; |
---|
1830 | | - dvddio-pex-supply = <&vdd_1v05>; |
---|
1831 | | - hvdd-usb-ss-pll-e-supply = <®_3v3>; |
---|
1832 | | - hvdd-usb-ss-supply = <®_3v3>; |
---|
| 1794 | + avddio-pex-supply = <®_1v05_vdd>; |
---|
| 1795 | + avdd-pll-erefe-supply = <®_1v05_avdd>; |
---|
| 1796 | + avdd-pll-utmip-supply = <®_1v8_vddio>; |
---|
| 1797 | + avdd-usb-ss-pll-supply = <®_1v05_vdd>; |
---|
| 1798 | + avdd-usb-supply = <®_module_3v3>; |
---|
| 1799 | + dvddio-pex-supply = <®_1v05_vdd>; |
---|
| 1800 | + hvdd-usb-ss-pll-e-supply = <®_module_3v3>; |
---|
| 1801 | + hvdd-usb-ss-supply = <®_module_3v3>; |
---|
1833 | 1802 | }; |
---|
1834 | 1803 | |
---|
1835 | 1804 | padctl@7009f000 { |
---|
| 1805 | + avdd-pll-utmip-supply = <®_1v8_vddio>; |
---|
| 1806 | + avdd-pll-erefe-supply = <®_1v05_avdd>; |
---|
| 1807 | + avdd-pex-pll-supply = <®_1v05_vdd>; |
---|
| 1808 | + hvdd-pex-pll-e-supply = <®_module_3v3>; |
---|
| 1809 | + |
---|
1836 | 1810 | pads { |
---|
1837 | 1811 | usb2 { |
---|
1838 | 1812 | status = "okay"; |
---|
1839 | 1813 | |
---|
1840 | 1814 | lanes { |
---|
1841 | 1815 | usb2-0 { |
---|
1842 | | - nvidia,function = "xusb"; |
---|
1843 | 1816 | status = "okay"; |
---|
| 1817 | + nvidia,function = "xusb"; |
---|
1844 | 1818 | }; |
---|
1845 | 1819 | |
---|
1846 | 1820 | usb2-1 { |
---|
1847 | | - nvidia,function = "xusb"; |
---|
1848 | 1821 | status = "okay"; |
---|
| 1822 | + nvidia,function = "xusb"; |
---|
1849 | 1823 | }; |
---|
1850 | 1824 | |
---|
1851 | 1825 | usb2-2 { |
---|
1852 | | - nvidia,function = "xusb"; |
---|
1853 | 1826 | status = "okay"; |
---|
| 1827 | + nvidia,function = "xusb"; |
---|
1854 | 1828 | }; |
---|
1855 | 1829 | }; |
---|
1856 | 1830 | }; |
---|
.. | .. |
---|
1860 | 1834 | |
---|
1861 | 1835 | lanes { |
---|
1862 | 1836 | pcie-0 { |
---|
1863 | | - nvidia,function = "usb3-ss"; |
---|
1864 | 1837 | status = "okay"; |
---|
| 1838 | + nvidia,function = "usb3-ss"; |
---|
1865 | 1839 | }; |
---|
1866 | 1840 | |
---|
1867 | 1841 | pcie-1 { |
---|
1868 | | - nvidia,function = "usb3-ss"; |
---|
1869 | 1842 | status = "okay"; |
---|
| 1843 | + nvidia,function = "usb3-ss"; |
---|
1870 | 1844 | }; |
---|
1871 | 1845 | |
---|
1872 | 1846 | pcie-2 { |
---|
1873 | | - nvidia,function = "pcie"; |
---|
1874 | 1847 | status = "okay"; |
---|
| 1848 | + nvidia,function = "pcie"; |
---|
1875 | 1849 | }; |
---|
1876 | 1850 | |
---|
1877 | 1851 | pcie-3 { |
---|
1878 | | - nvidia,function = "pcie"; |
---|
1879 | 1852 | status = "okay"; |
---|
| 1853 | + nvidia,function = "pcie"; |
---|
1880 | 1854 | }; |
---|
1881 | 1855 | |
---|
1882 | 1856 | pcie-4 { |
---|
1883 | | - nvidia,function = "pcie"; |
---|
1884 | 1857 | status = "okay"; |
---|
| 1858 | + nvidia,function = "pcie"; |
---|
1885 | 1859 | }; |
---|
1886 | 1860 | }; |
---|
1887 | 1861 | }; |
---|
.. | .. |
---|
1891 | 1865 | |
---|
1892 | 1866 | lanes { |
---|
1893 | 1867 | sata-0 { |
---|
1894 | | - nvidia,function = "sata"; |
---|
1895 | 1868 | status = "okay"; |
---|
| 1869 | + nvidia,function = "sata"; |
---|
1896 | 1870 | }; |
---|
1897 | 1871 | }; |
---|
1898 | 1872 | }; |
---|
.. | .. |
---|
1903 | 1877 | usb2-0 { |
---|
1904 | 1878 | status = "okay"; |
---|
1905 | 1879 | mode = "otg"; |
---|
1906 | | - |
---|
1907 | 1880 | vbus-supply = <®_usbo1_vbus>; |
---|
1908 | 1881 | }; |
---|
1909 | 1882 | |
---|
.. | .. |
---|
1911 | 1884 | usb2-1 { |
---|
1912 | 1885 | status = "okay"; |
---|
1913 | 1886 | mode = "host"; |
---|
1914 | | - |
---|
1915 | 1887 | vbus-supply = <®_usbh_vbus>; |
---|
1916 | 1888 | }; |
---|
1917 | 1889 | |
---|
.. | .. |
---|
1919 | 1891 | usb2-2 { |
---|
1920 | 1892 | status = "okay"; |
---|
1921 | 1893 | mode = "host"; |
---|
1922 | | - |
---|
1923 | 1894 | vbus-supply = <®_usbh_vbus>; |
---|
1924 | 1895 | }; |
---|
1925 | 1896 | |
---|
1926 | 1897 | usb3-0 { |
---|
1927 | | - nvidia,usb2-companion = <2>; |
---|
1928 | 1898 | status = "okay"; |
---|
| 1899 | + nvidia,usb2-companion = <2>; |
---|
| 1900 | + vbus-supply = <®_usbh_vbus>; |
---|
1929 | 1901 | }; |
---|
1930 | 1902 | |
---|
1931 | 1903 | usb3-1 { |
---|
1932 | | - nvidia,usb2-companion = <0>; |
---|
1933 | 1904 | status = "okay"; |
---|
| 1905 | + nvidia,usb2-companion = <0>; |
---|
| 1906 | + vbus-supply = <®_usbo1_vbus>; |
---|
1934 | 1907 | }; |
---|
1935 | 1908 | }; |
---|
1936 | 1909 | }; |
---|
1937 | 1910 | |
---|
1938 | 1911 | /* eMMC */ |
---|
1939 | | - sdhci@700b0600 { |
---|
| 1912 | + mmc@700b0600 { |
---|
1940 | 1913 | status = "okay"; |
---|
1941 | 1914 | bus-width = <8>; |
---|
1942 | 1915 | non-removable; |
---|
| 1916 | + vmmc-supply = <®_module_3v3>; /* VCC */ |
---|
| 1917 | + vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ |
---|
| 1918 | + mmc-ddr-1_8v; |
---|
1943 | 1919 | }; |
---|
1944 | 1920 | |
---|
1945 | 1921 | /* CPU DFLL clock */ |
---|
1946 | 1922 | clock@70110000 { |
---|
1947 | 1923 | status = "okay"; |
---|
1948 | | - vdd-cpu-supply = <&vdd_cpu>; |
---|
1949 | 1924 | nvidia,i2c-fs-rate = <400000>; |
---|
| 1925 | + vdd-cpu-supply = <®_vdd_cpu>; |
---|
1950 | 1926 | }; |
---|
1951 | 1927 | |
---|
1952 | 1928 | ahub@70300000 { |
---|
.. | .. |
---|
1955 | 1931 | }; |
---|
1956 | 1932 | }; |
---|
1957 | 1933 | |
---|
1958 | | - clocks { |
---|
1959 | | - compatible = "simple-bus"; |
---|
1960 | | - #address-cells = <1>; |
---|
1961 | | - #size-cells = <0>; |
---|
1962 | | - |
---|
1963 | | - clk32k_in: clock@0 { |
---|
1964 | | - compatible = "fixed-clock"; |
---|
1965 | | - reg = <0>; |
---|
1966 | | - #clock-cells = <0>; |
---|
1967 | | - clock-frequency = <32768>; |
---|
1968 | | - }; |
---|
| 1934 | + clk32k_in: osc3 { |
---|
| 1935 | + compatible = "fixed-clock"; |
---|
| 1936 | + #clock-cells = <0>; |
---|
| 1937 | + clock-frequency = <32768>; |
---|
1969 | 1938 | }; |
---|
1970 | 1939 | |
---|
1971 | 1940 | cpus { |
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1972 | 1941 | cpu@0 { |
---|
1973 | | - vdd-cpu-supply = <&vdd_cpu>; |
---|
| 1942 | + vdd-cpu-supply = <®_vdd_cpu>; |
---|
1974 | 1943 | }; |
---|
1975 | 1944 | }; |
---|
1976 | 1945 | |
---|
.. | .. |
---|
1980 | 1949 | regulator-min-microvolt = <1050000>; |
---|
1981 | 1950 | regulator-max-microvolt = <1050000>; |
---|
1982 | 1951 | gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; |
---|
1983 | | - vin-supply = <&vdd_1v05>; |
---|
| 1952 | + vin-supply = <®_1v05_vdd>; |
---|
1984 | 1953 | }; |
---|
1985 | 1954 | |
---|
1986 | 1955 | reg_3v3_mxm: regulator-3v3-mxm { |
---|
.. | .. |
---|
1992 | 1961 | regulator-boot-on; |
---|
1993 | 1962 | }; |
---|
1994 | 1963 | |
---|
1995 | | - reg_3v3: regulator-3v3 { |
---|
| 1964 | + reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { |
---|
| 1965 | + compatible = "regulator-fixed"; |
---|
| 1966 | + regulator-name = "+V3.3_AVDD_HDMI"; |
---|
| 1967 | + regulator-min-microvolt = <3300000>; |
---|
| 1968 | + regulator-max-microvolt = <3300000>; |
---|
| 1969 | + vin-supply = <®_1v05_vdd>; |
---|
| 1970 | + }; |
---|
| 1971 | + |
---|
| 1972 | + reg_module_3v3: regulator-module-3v3 { |
---|
1996 | 1973 | compatible = "regulator-fixed"; |
---|
1997 | 1974 | regulator-name = "+V3.3"; |
---|
1998 | 1975 | regulator-min-microvolt = <3300000>; |
---|
.. | .. |
---|
2005 | 1982 | vin-supply = <®_3v3_mxm>; |
---|
2006 | 1983 | }; |
---|
2007 | 1984 | |
---|
2008 | | - reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { |
---|
| 1985 | + reg_module_3v3_audio: regulator-module-3v3-audio { |
---|
2009 | 1986 | compatible = "regulator-fixed"; |
---|
2010 | | - regulator-name = "+V3.3_AVDD_HDMI"; |
---|
| 1987 | + regulator-name = "+V3.3_AUDIO_AVDD_S"; |
---|
2011 | 1988 | regulator-min-microvolt = <3300000>; |
---|
2012 | 1989 | regulator-max-microvolt = <3300000>; |
---|
2013 | | - vin-supply = <&vdd_1v05>; |
---|
| 1990 | + regulator-always-on; |
---|
2014 | 1991 | }; |
---|
2015 | 1992 | |
---|
2016 | 1993 | sound { |
---|
.. | .. |
---|
2025 | 2002 | nvidia,audio-codec = <&sgtl5000>; |
---|
2026 | 2003 | clocks = <&tegra_car TEGRA124_CLK_PLL_A>, |
---|
2027 | 2004 | <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, |
---|
2028 | | - <&tegra_car TEGRA124_CLK_EXTERN1>; |
---|
| 2005 | + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
---|
2029 | 2006 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
---|
| 2007 | + |
---|
| 2008 | + assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, |
---|
| 2009 | + <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; |
---|
| 2010 | + |
---|
| 2011 | + assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, |
---|
| 2012 | + <&tegra_car TEGRA124_CLK_EXTERN1>; |
---|
2030 | 2013 | }; |
---|
2031 | 2014 | |
---|
2032 | 2015 | thermal-zones { |
---|
.. | .. |
---|
2064 | 2047 | |
---|
2065 | 2048 | &gpio { |
---|
2066 | 2049 | /* I210 Gigabit Ethernet Controller Reset */ |
---|
2067 | | - lan_reset_n { |
---|
| 2050 | + lan-reset-n { |
---|
2068 | 2051 | gpio-hog; |
---|
2069 | 2052 | gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; |
---|
2070 | 2053 | output-high; |
---|
.. | .. |
---|
2072 | 2055 | }; |
---|
2073 | 2056 | |
---|
2074 | 2057 | /* Control MXM3 pin 26 Reset Module Output Carrier Input */ |
---|
2075 | | - reset_moci_ctrl { |
---|
| 2058 | + reset-moci-ctrl { |
---|
2076 | 2059 | gpio-hog; |
---|
2077 | 2060 | gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; |
---|
2078 | 2061 | output-high; |
---|