add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/sun8i-v3s.dtsi
..
..
@@ -43,11 +43,27 @@
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
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 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
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+#include <dt-bindings/clock/sun8i-de2.h>
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 / {
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 	#address-cells = <1>;
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 	#size-cells = <1>;
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 	interrupt-parent = <&gic>;
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+
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+	chosen {
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		ranges;
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+
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+		framebuffer-lcd {
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+			compatible = "allwinner,simple-framebuffer",
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+				     "simple-framebuffer";
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+			allwinner,pipeline = "mixer0-lcd0";
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+			clocks = <&display_clocks CLK_MIXER0>,
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+				 <&ccu CLK_TCON0>;
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+			status = "disabled";
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+		};
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+	};
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67
 
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 	cpus {
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 		#address-cells = <1>;
..
..
@@ -84,6 +100,7 @@
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 			#clock-cells = <0>;
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 			compatible = "fixed-clock";
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 			clock-frequency = <24000000>;
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+			clock-accuracy = <50000>;
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 			clock-output-names = "osc24M";
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 		};
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..
..
@@ -91,7 +108,8 @@
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 			#clock-cells = <0>;
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 			compatible = "fixed-clock";
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 			clock-frequency = <32768>;
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-			clock-output-names = "osc32k";
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+			clock-accuracy = <50000>;
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+			clock-output-names = "ext-osc32k";
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 		};
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 	};
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115
 
..
..
@@ -103,11 +121,11 @@
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121
 
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 		display_clocks: clock@1000000 {
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 			compatible = "allwinner,sun8i-v3s-de2-clk";
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-			reg = <0x01000000 0x100000>;
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-			clocks = <&ccu CLK_DE>,
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-				 <&ccu CLK_BUS_DE>;
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-			clock-names = "mod",
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-				      "bus";
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+			reg = <0x01000000 0x10000>;
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+			clocks = <&ccu CLK_BUS_DE>,
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+				 <&ccu CLK_DE>;
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+			clock-names = "bus",
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+				      "mod";
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 			resets = <&ccu RST_BUS_DE>;
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 			#clock-cells = <1>;
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 			#reset-cells = <1>;
..
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@@ -121,24 +139,28 @@
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 			clock-names = "bus",
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 				      "mod";
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 			resets = <&display_clocks 0>;
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-			assigned-clocks = <&display_clocks 6>;
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-			assigned-clock-rates = <150000000>;
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142
 
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 			ports {
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 				#address-cells = <1>;
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 				#size-cells = <0>;
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146
 
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 				mixer0_out: port@1 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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 					reg = <1>;
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-					mixer0_out_tcon0: endpoint@0 {
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-						reg = <0>;
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+					mixer0_out_tcon0: endpoint {
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 						remote-endpoint = <&tcon0_in_mixer0>;
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 					};
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 				};
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 			};
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+		};
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+
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+		syscon: system-control@1c00000 {
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+			compatible = "allwinner,sun8i-v3s-system-control",
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+				     "allwinner,sun8i-h3-system-control";
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+			reg = <0x01c00000 0x1000>;
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+			#address-cells = <1>;
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+			#size-cells = <1>;
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+			ranges;
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 		};
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165
 
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 		tcon0: lcd-controller@1c0c000 {
..
..
@@ -150,6 +172,7 @@
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 			clock-names = "ahb",
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 				      "tcon-ch0";
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 			clock-output-names = "tcon-pixel-clock";
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+			#clock-cells = <0>;
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 			resets = <&ccu RST_BUS_TCON0>;
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 			reset-names = "lcd";
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 			status = "disabled";
..
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@@ -159,12 +182,9 @@
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 				#size-cells = <0>;
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183
 
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 				tcon0_in: port@0 {
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-					#address-cells = <1>;
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-					#size-cells = <0>;
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185
 					reg = <0>;
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186
 
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-					tcon0_in_mixer0: endpoint@0 {
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-						reg = <0>;
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+					tcon0_in_mixer0: endpoint {
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 						remote-endpoint = <&mixer0_out_tcon0>;
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 					};
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 				};
..
..
@@ -192,6 +212,8 @@
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 			resets = <&ccu RST_BUS_MMC0>;
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 			reset-names = "ahb";
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 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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+			pinctrl-names = "default";
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+			pinctrl-0 = <&mmc0_pins>;
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 			status = "disabled";
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 			#address-cells = <1>;
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 			#size-cells = <0>;
..
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@@ -237,6 +259,17 @@
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 			#size-cells = <0>;
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 		};
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261
 
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+		crypto@1c15000 {
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+			compatible = "allwinner,sun8i-v3s-crypto",
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+				     "allwinner,sun8i-a33-crypto";
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+			reg = <0x01c15000 0x1000>;
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+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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+			clock-names = "ahb", "mod";
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+			resets = <&ccu RST_BUS_CE>;
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+			reset-names = "ahb";
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+		};
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+
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 		usb_otg: usb@1c19000 {
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 			compatible = "allwinner,sun8i-h3-musb";
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 			reg = <0x01c19000 0x0400>;
..
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@@ -267,17 +300,20 @@
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 		ccu: clock@1c20000 {
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 			compatible = "allwinner,sun8i-v3s-ccu";
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 			reg = <0x01c20000 0x400>;
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-			clocks = <&osc24M>, <&osc32k>;
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+			clocks = <&osc24M>, <&rtc 0>;
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 			clock-names = "hosc", "losc";
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 			#clock-cells = <1>;
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 			#reset-cells = <1>;
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 		};
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 		rtc: rtc@1c20400 {
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-			compatible = "allwinner,sun6i-a31-rtc";
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+			#clock-cells = <1>;
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+			compatible = "allwinner,sun8i-v3-rtc";
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 			reg = <0x01c20400 0x54>;
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 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&osc32k>;
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+			clock-output-names = "osc32k", "osc32k-out";
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 		};
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318
 
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 		pio: pinctrl@1c20800 {
..
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@@ -285,21 +321,46 @@
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 			reg = <0x01c20800 0x400>;
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 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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 				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
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+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
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 			clock-names = "apb", "hosc", "losc";
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 			gpio-controller;
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 			#gpio-cells = <3>;
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 			interrupt-controller;
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 			#interrupt-cells = <3>;
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+			/omit-if-no-ref/
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+			csi1_8bit_pins: csi1-8bit-pins {
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+				pins = "PE0", "PE2", "PE3", "PE8", "PE9",
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+				       "PE10", "PE11", "PE12", "PE13", "PE14",
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+				       "PE15";
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+				function = "csi";
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+			};
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+
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+			/omit-if-no-ref/
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+			csi1_mclk_pin: csi1-mclk-pin {
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+				pins = "PE1";
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+				function = "csi";
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+			};
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+
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 			i2c0_pins: i2c0-pins {
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 				pins = "PB6", "PB7";
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 				function = "i2c0";
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 			};
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+			/omit-if-no-ref/
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+			i2c1_pe_pins: i2c1-pe-pins {
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+				pins = "PE21", "PE22";
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+				function = "i2c1";
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+			};
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+
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 			uart0_pb_pins: uart0-pb-pins {
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 				pins = "PB8", "PB9";
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 				function = "uart0";
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+			};
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+
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+			uart2_pins: uart2-pins {
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+				pins = "PB0", "PB1";
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+				function = "uart2";
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 			};
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 			mmc0_pins: mmc0-pins {
..
..
@@ -325,10 +386,11 @@
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386
 		};
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387
 
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 		timer@1c20c00 {
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-			compatible = "allwinner,sun4i-a10-timer";
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+			compatible = "allwinner,sun8i-v3s-timer";
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 			reg = <0x01c20c00 0xa0>;
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 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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-				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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+				     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&osc24M>;
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 		};
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..
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@@ -336,6 +398,7 @@
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 			compatible = "allwinner,sun6i-a31-wdt";
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 			reg = <0x01c20ca0 0x20>;
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 			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&osc24M>;
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402
 		};
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403
 
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 		lradc: lradc@1c22800 {
..
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@@ -375,6 +438,8 @@
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 			reg-io-width = <4>;
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 			clocks = <&ccu CLK_BUS_UART2>;
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 			resets = <&ccu RST_BUS_UART2>;
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+			pinctrl-0 = <&uart2_pins>;
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+			pinctrl-names = "default";
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 			status = "disabled";
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 		};
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..
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@@ -402,6 +467,49 @@
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 			#size-cells = <0>;
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 		};
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469
 
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+		emac: ethernet@1c30000 {
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+			compatible = "allwinner,sun8i-v3s-emac";
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+			syscon = <&syscon>;
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+			reg = <0x01c30000 0x10000>;
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+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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+			interrupt-names = "macirq";
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+			resets = <&ccu RST_BUS_EMAC>;
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+			reset-names = "stmmaceth";
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+			clocks = <&ccu CLK_BUS_EMAC>;
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+			clock-names = "stmmaceth";
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+			phy-handle = <&int_mii_phy>;
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+			phy-mode = "mii";
482
+			status = "disabled";
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+
484
+			mdio: mdio {
485
+				#address-cells = <1>;
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+				#size-cells = <0>;
487
+				compatible = "snps,dwmac-mdio";
488
+			};
489
+
490
+			mdio_mux: mdio-mux {
491
+				compatible = "allwinner,sun8i-h3-mdio-mux";
492
+				#address-cells = <1>;
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+				#size-cells = <0>;
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+
495
+				mdio-parent-bus = <&mdio>;
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+				/* Only one MDIO is usable at the time */
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+				internal_mdio: mdio@1 {
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+					compatible = "allwinner,sun8i-h3-mdio-internal";
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+					reg = <1>;
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+					#address-cells = <1>;
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+					#size-cells = <0>;
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+
503
+					int_mii_phy: ethernet-phy@1 {
504
+						compatible = "ethernet-phy-ieee802.3-c22";
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+						reg = <1>;
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+						clocks = <&ccu CLK_BUS_EPHY>;
507
+						resets = <&ccu RST_BUS_EPHY>;
508
+					};
509
+				};
510
+			};
511
+		};
512
+
405
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 		spi0: spi@1c68000 {
406
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 			compatible = "allwinner,sun8i-h3-spi";
407
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 			reg = <0x01c68000 0x1000>;
..
..
@@ -417,7 +525,7 @@
417
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 		};
418
526
 
419
527
 		gic: interrupt-controller@1c81000 {
420
-			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
528
+			compatible = "arm,gic-400";
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529
 			reg = <0x01c81000 0x1000>,
422
530
 			      <0x01c82000 0x2000>,
423
531
 			      <0x01c84000 0x2000>,
..
..
@@ -426,5 +534,17 @@
426
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 			#interrupt-cells = <3>;
427
535
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
428
536
 		};
537
+
538
+		csi1: camera@1cb4000 {
539
+			compatible = "allwinner,sun8i-v3s-csi";
540
+			reg = <0x01cb4000 0x3000>;
541
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
542
+			clocks = <&ccu CLK_BUS_CSI>,
543
+				 <&ccu CLK_CSI1_SCLK>,
544
+				 <&ccu CLK_DRAM_CSI>;
545
+			clock-names = "bus", "mod", "ram";
546
+			resets = <&ccu RST_BUS_CSI>;
547
+			status = "disabled";
548
+		};
429
549
 	};
430
550
 };