add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/sun8i-r40.dtsi
..
..
@@ -44,8 +44,10 @@
44
44
 #include <dt-bindings/interrupt-controller/arm-gic.h>
45
45
 #include <dt-bindings/clock/sun8i-de2.h>
46
46
 #include <dt-bindings/clock/sun8i-r40-ccu.h>
47
+#include <dt-bindings/clock/sun8i-tcon-top.h>
47
48
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
48
49
 #include <dt-bindings/reset/sun8i-de2.h>
50
+#include <dt-bindings/thermal/thermal.h>
49
51
 
50
52
 / {
51
53
 	#address-cells = <1>;
..
..
@@ -61,6 +63,7 @@
61
63
 			#clock-cells = <0>;
62
64
 			compatible = "fixed-clock";
63
65
 			clock-frequency = <24000000>;
66
+			clock-accuracy = <50000>;
64
67
 			clock-output-names = "osc24M";
65
68
 		};
66
69
 
..
..
@@ -68,7 +71,8 @@
68
71
 			#clock-cells = <0>;
69
72
 			compatible = "fixed-clock";
70
73
 			clock-frequency = <32768>;
71
-			clock-output-names = "osc32k";
74
+			clock-accuracy = <20000>;
75
+			clock-output-names = "ext-osc32k";
72
76
 		};
73
77
 	};
74
78
 
..
..
@@ -76,25 +80,25 @@
76
80
 		#address-cells = <1>;
77
81
 		#size-cells = <0>;
78
82
 
79
-		cpu@0 {
83
+		cpu0: cpu@0 {
80
84
 			compatible = "arm,cortex-a7";
81
85
 			device_type = "cpu";
82
86
 			reg = <0>;
83
87
 		};
84
88
 
85
-		cpu@1 {
89
+		cpu1: cpu@1 {
86
90
 			compatible = "arm,cortex-a7";
87
91
 			device_type = "cpu";
88
92
 			reg = <1>;
89
93
 		};
90
94
 
91
-		cpu@2 {
95
+		cpu2: cpu@2 {
92
96
 			compatible = "arm,cortex-a7";
93
97
 			device_type = "cpu";
94
98
 			reg = <2>;
95
99
 		};
96
100
 
97
-		cpu@3 {
101
+		cpu3: cpu@3 {
98
102
 			compatible = "arm,cortex-a7";
99
103
 			device_type = "cpu";
100
104
 			reg = <3>;
..
..
@@ -107,6 +111,22 @@
107
111
 		status = "disabled";
108
112
 	};
109
113
 
114
+	thermal-zones {
115
+		cpu_thermal: cpu0-thermal {
116
+			/* milliseconds */
117
+			polling-delay-passive = <0>;
118
+			polling-delay = <0>;
119
+			thermal-sensors = <&ths 0>;
120
+		};
121
+
122
+		gpu_thermal: gpu-thermal {
123
+			/* milliseconds */
124
+			polling-delay-passive = <0>;
125
+			polling-delay = <0>;
126
+			thermal-sensors = <&ths 1>;
127
+		};
128
+	};
129
+
110
130
 	soc {
111
131
 		compatible = "simple-bus";
112
132
 		#address-cells = <1>;
..
..
@@ -116,11 +136,11 @@
116
136
 		display_clocks: clock@1000000 {
117
137
 			compatible = "allwinner,sun8i-r40-de2-clk",
118
138
 				     "allwinner,sun8i-h3-de2-clk";
119
-			reg = <0x01000000 0x100000>;
120
-			clocks = <&ccu CLK_DE>,
121
-				 <&ccu CLK_BUS_DE>;
122
-			clock-names = "mod",
123
-				      "bus";
139
+			reg = <0x01000000 0x10000>;
140
+			clocks = <&ccu CLK_BUS_DE>,
141
+				 <&ccu CLK_DE>;
142
+			clock-names = "bus",
143
+				      "mod";
124
144
 			resets = <&ccu RST_BUS_DE>;
125
145
 			#clock-cells = <1>;
126
146
 			#reset-cells = <1>;
..
..
@@ -170,12 +190,98 @@
170
190
 			};
171
191
 		};
172
192
 
193
+		syscon: system-control@1c00000 {
194
+			compatible = "allwinner,sun8i-r40-system-control",
195
+				     "allwinner,sun4i-a10-system-control";
196
+			reg = <0x01c00000 0x30>;
197
+			#address-cells = <1>;
198
+			#size-cells = <1>;
199
+			ranges;
200
+
201
+			sram_c: sram@1d00000 {
202
+				compatible = "mmio-sram";
203
+				reg = <0x01d00000 0xd0000>;
204
+				#address-cells = <1>;
205
+				#size-cells = <1>;
206
+				ranges = <0 0x01d00000 0xd0000>;
207
+
208
+				ve_sram: sram-section@0 {
209
+					compatible = "allwinner,sun8i-r40-sram-c1",
210
+						     "allwinner,sun4i-a10-sram-c1";
211
+					reg = <0x000000 0x80000>;
212
+				};
213
+			};
214
+		};
215
+
173
216
 		nmi_intc: interrupt-controller@1c00030 {
174
217
 			compatible = "allwinner,sun7i-a20-sc-nmi";
175
218
 			interrupt-controller;
176
219
 			#interrupt-cells = <2>;
177
220
 			reg = <0x01c00030 0x0c>;
178
221
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
222
+		};
223
+
224
+		dma: dma-controller@1c02000 {
225
+			compatible = "allwinner,sun8i-r40-dma",
226
+				     "allwinner,sun50i-a64-dma";
227
+			reg = <0x01c02000 0x1000>;
228
+			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
229
+			clocks = <&ccu CLK_BUS_DMA>;
230
+			dma-channels = <16>;
231
+			dma-requests = <31>;
232
+			resets = <&ccu RST_BUS_DMA>;
233
+			#dma-cells = <1>;
234
+		};
235
+
236
+		spi0: spi@1c05000 {
237
+			compatible = "allwinner,sun8i-r40-spi",
238
+				     "allwinner,sun8i-h3-spi";
239
+			reg = <0x01c05000 0x1000>;
240
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
241
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
242
+			clock-names = "ahb", "mod";
243
+			resets = <&ccu RST_BUS_SPI0>;
244
+			status = "disabled";
245
+			#address-cells = <1>;
246
+			#size-cells = <0>;
247
+		};
248
+
249
+		spi1: spi@1c06000 {
250
+			compatible = "allwinner,sun8i-r40-spi",
251
+				     "allwinner,sun8i-h3-spi";
252
+			reg = <0x01c06000 0x1000>;
253
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
254
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
255
+			clock-names = "ahb", "mod";
256
+			resets = <&ccu RST_BUS_SPI1>;
257
+			status = "disabled";
258
+			#address-cells = <1>;
259
+			#size-cells = <0>;
260
+		};
261
+
262
+		csi0: csi@1c09000 {
263
+			compatible = "allwinner,sun8i-r40-csi0",
264
+				     "allwinner,sun7i-a20-csi0";
265
+			reg = <0x01c09000 0x1000>;
266
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
267
+			clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
268
+				 <&ccu CLK_DRAM_CSI0>;
269
+			clock-names = "bus", "isp", "ram";
270
+			resets = <&ccu RST_BUS_CSI0>;
271
+			interconnects = <&mbus 5>;
272
+			interconnect-names = "dma-mem";
273
+			status = "disabled";
274
+		};
275
+
276
+		video-codec@1c0e000 {
277
+			compatible = "allwinner,sun8i-r40-video-engine";
278
+			reg = <0x01c0e000 0x1000>;
279
+			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
280
+			<&ccu CLK_DRAM_VE>;
281
+			clock-names = "ahb", "mod", "ram";
282
+			resets = <&ccu RST_BUS_VE>;
283
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
284
+			allwinner,sram = <&ve_sram 1>;
179
285
 		};
180
286
 
181
287
 		mmc0: mmc@1c0f000 {
..
..
@@ -264,6 +370,38 @@
264
370
 			#phy-cells = <1>;
265
371
 		};
266
372
 
373
+		crypto: crypto@1c15000 {
374
+			compatible = "allwinner,sun8i-r40-crypto";
375
+			reg = <0x01c15000 0x1000>;
376
+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
377
+			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
378
+			clock-names = "bus", "mod";
379
+			resets = <&ccu RST_BUS_CE>;
380
+		};
381
+
382
+		spi2: spi@1c17000 {
383
+			compatible = "allwinner,sun8i-r40-spi",
384
+				     "allwinner,sun8i-h3-spi";
385
+			reg = <0x01c17000 0x1000>;
386
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
387
+			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
388
+			clock-names = "ahb", "mod";
389
+			resets = <&ccu RST_BUS_SPI2>;
390
+			status = "disabled";
391
+			#address-cells = <1>;
392
+			#size-cells = <0>;
393
+		};
394
+
395
+		ahci: sata@1c18000 {
396
+			compatible = "allwinner,sun8i-r40-ahci";
397
+			reg = <0x01c18000 0x1000>;
398
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
399
+			clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
400
+			resets = <&ccu RST_BUS_SATA>;
401
+			reset-names = "ahci";
402
+			status = "disabled";
403
+		};
404
+
267
405
 		ehci1: usb@1c19000 {
268
406
 			compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
269
407
 			reg = <0x01c19000 0x100>;
..
..
@@ -310,25 +448,66 @@
310
448
 			status = "disabled";
311
449
 		};
312
450
 
451
+		spi3: spi@1c1f000 {
452
+			compatible = "allwinner,sun8i-r40-spi",
453
+				     "allwinner,sun8i-h3-spi";
454
+			reg = <0x01c1f000 0x1000>;
455
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
456
+			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
457
+			clock-names = "ahb", "mod";
458
+			resets = <&ccu RST_BUS_SPI3>;
459
+			status = "disabled";
460
+			#address-cells = <1>;
461
+			#size-cells = <0>;
462
+		};
463
+
313
464
 		ccu: clock@1c20000 {
314
465
 			compatible = "allwinner,sun8i-r40-ccu";
315
466
 			reg = <0x01c20000 0x400>;
316
-			clocks = <&osc24M>, <&osc32k>;
467
+			clocks = <&osc24M>, <&rtc 0>;
317
468
 			clock-names = "hosc", "losc";
318
469
 			#clock-cells = <1>;
319
470
 			#reset-cells = <1>;
471
+		};
472
+
473
+		rtc: rtc@1c20400 {
474
+			compatible = "allwinner,sun8i-r40-rtc";
475
+			reg = <0x01c20400 0x400>;
476
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
477
+			clock-output-names = "osc32k", "osc32k-out";
478
+			clocks = <&osc32k>;
479
+			#clock-cells = <1>;
320
480
 		};
321
481
 
322
482
 		pio: pinctrl@1c20800 {
323
483
 			compatible = "allwinner,sun8i-r40-pinctrl";
324
484
 			reg = <0x01c20800 0x400>;
325
485
 			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
326
-			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
486
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
327
487
 			clock-names = "apb", "hosc", "losc";
328
488
 			gpio-controller;
329
489
 			interrupt-controller;
330
490
 			#interrupt-cells = <3>;
331
491
 			#gpio-cells = <3>;
492
+
493
+			clk_out_a_pin: clk-out-a-pin {
494
+				pins = "PI12";
495
+				function = "clk_out_a";
496
+			};
497
+
498
+			/omit-if-no-ref/
499
+			csi0_8bits_pins: csi0-8bits-pins {
500
+				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
501
+				       "PE6", "PE7", "PE8", "PE9", "PE10",
502
+				       "PE11";
503
+				function = "csi0";
504
+			};
505
+
506
+			/omit-if-no-ref/
507
+			csi0_mclk_pin: csi0-mclk-pin {
508
+				pins = "PE1";
509
+				function = "csi0";
510
+			};
332
511
 
333
512
 			gmac_rgmii_pins: gmac-rgmii-pins {
334
513
 				pins = "PA0", "PA1", "PA2", "PA3",
..
..
@@ -346,6 +525,36 @@
346
525
 			i2c0_pins: i2c0-pins {
347
526
 				pins = "PB0", "PB1";
348
527
 				function = "i2c0";
528
+			};
529
+
530
+			i2c1_pins: i2c1-pins {
531
+				pins = "PB18", "PB19";
532
+				function = "i2c1";
533
+			};
534
+
535
+			i2c2_pins: i2c2-pins {
536
+				pins = "PB20", "PB21";
537
+				function = "i2c2";
538
+			};
539
+
540
+			i2c3_pins: i2c3-pins {
541
+				pins = "PI0", "PI1";
542
+				function = "i2c3";
543
+			};
544
+
545
+			i2c4_pins: i2c4-pins {
546
+				pins = "PI2", "PI3";
547
+				function = "i2c4";
548
+			};
549
+
550
+			ir0_pins: ir0-pins {
551
+				pins = "PB4";
552
+				function = "ir0";
553
+			};
554
+
555
+			ir1_pins: ir1-pins {
556
+				pins = "PB23";
557
+				function = "ir1";
349
558
 			};
350
559
 
351
560
 			mmc0_pins: mmc0-pins {
..
..
@@ -373,15 +582,94 @@
373
582
 				bias-pull-up;
374
583
 			};
375
584
 
585
+			/omit-if-no-ref/
586
+			spi0_pc_pins: spi0-pc-pins {
587
+				pins = "PC0", "PC1", "PC2";
588
+				function = "spi0";
589
+			};
590
+
591
+			/omit-if-no-ref/
592
+			spi0_cs0_pc_pin: spi0-cs0-pc-pin {
593
+				pins = "PC23";
594
+				function = "spi0";
595
+			};
596
+
597
+			/omit-if-no-ref/
598
+			spi1_pi_pins: spi1-pi-pins {
599
+				pins = "PI17", "PI18", "PI19";
600
+				function = "spi1";
601
+			};
602
+
603
+			/omit-if-no-ref/
604
+			spi1_cs0_pi_pin: spi1-cs0-pi-pin {
605
+				pins = "PI16";
606
+				function = "spi1";
607
+			};
608
+
609
+			/omit-if-no-ref/
610
+			spi1_cs1_pi_pin: spi1-cs1-pi-pin {
611
+				pins = "PI15";
612
+				function = "spi1";
613
+			};
614
+
376
615
 			uart0_pb_pins: uart0-pb-pins {
377
616
 				pins = "PB22", "PB23";
378
617
 				function = "uart0";
618
+			};
619
+
620
+			uart3_pg_pins: uart3-pg-pins {
621
+				pins = "PG6", "PG7";
622
+				function = "uart3";
623
+			};
624
+
625
+			uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins {
626
+				pins = "PG8", "PG9";
627
+				function = "uart3";
379
628
 			};
380
629
 		};
381
630
 
382
631
 		wdt: watchdog@1c20c90 {
383
632
 			compatible = "allwinner,sun4i-a10-wdt";
384
633
 			reg = <0x01c20c90 0x10>;
634
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
635
+			clocks = <&osc24M>;
636
+		};
637
+
638
+		ir0: ir@1c21800 {
639
+			compatible = "allwinner,sun8i-r40-ir",
640
+				     "allwinner,sun6i-a31-ir";
641
+			reg = <0x01c21800 0x400>;
642
+			pinctrl-0 = <&ir0_pins>;
643
+			pinctrl-names = "default";
644
+			clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>;
645
+			clock-names = "apb", "ir";
646
+			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
647
+			resets = <&ccu RST_BUS_IR0>;
648
+			status = "disabled";
649
+		};
650
+
651
+		ir1: ir@1c21c00 {
652
+			compatible = "allwinner,sun8i-r40-ir",
653
+				     "allwinner,sun6i-a31-ir";
654
+			reg = <0x01c21c00 0x400>;
655
+			pinctrl-0 = <&ir1_pins>;
656
+			pinctrl-names = "default";
657
+			clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>;
658
+			clock-names = "apb", "ir";
659
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
660
+			resets = <&ccu RST_BUS_IR1>;
661
+			status = "disabled";
662
+		};
663
+
664
+		ths: thermal-sensor@1c24c00 {
665
+			compatible = "allwinner,sun8i-r40-ths";
666
+			reg = <0x01c24c00 0x100>;
667
+			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
668
+			clock-names = "bus", "mod";
669
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
670
+			resets = <&ccu RST_BUS_THS>;
671
+			/* TODO: add nvmem-cells for calibration */
672
+			#thermal-sensor-cells = <1>;
385
673
 		};
386
674
 
387
675
 		uart0: serial@1c28000 {
..
..
@@ -491,6 +779,8 @@
491
779
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
492
780
 			clocks = <&ccu CLK_BUS_I2C1>;
493
781
 			resets = <&ccu RST_BUS_I2C1>;
782
+			pinctrl-0 = <&i2c1_pins>;
783
+			pinctrl-names = "default";
494
784
 			status = "disabled";
495
785
 			#address-cells = <1>;
496
786
 			#size-cells = <0>;
..
..
@@ -502,6 +792,8 @@
502
792
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
503
793
 			clocks = <&ccu CLK_BUS_I2C2>;
504
794
 			resets = <&ccu RST_BUS_I2C2>;
795
+			pinctrl-0 = <&i2c2_pins>;
796
+			pinctrl-names = "default";
505
797
 			status = "disabled";
506
798
 			#address-cells = <1>;
507
799
 			#size-cells = <0>;
..
..
@@ -513,6 +805,8 @@
513
805
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
514
806
 			clocks = <&ccu CLK_BUS_I2C3>;
515
807
 			resets = <&ccu RST_BUS_I2C3>;
808
+			pinctrl-0 = <&i2c3_pins>;
809
+			pinctrl-names = "default";
516
810
 			status = "disabled";
517
811
 			#address-cells = <1>;
518
812
 			#size-cells = <0>;
..
..
@@ -524,9 +818,33 @@
524
818
 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
525
819
 			clocks = <&ccu CLK_BUS_I2C4>;
526
820
 			resets = <&ccu RST_BUS_I2C4>;
821
+			pinctrl-0 = <&i2c4_pins>;
822
+			pinctrl-names = "default";
527
823
 			status = "disabled";
528
824
 			#address-cells = <1>;
529
825
 			#size-cells = <0>;
826
+		};
827
+
828
+		mali: gpu@1c40000 {
829
+			compatible = "allwinner,sun8i-r40-mali", "arm,mali-400";
830
+			reg = <0x01c40000 0x10000>;
831
+			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
832
+				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
833
+				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
834
+				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
835
+				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
836
+				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
837
+				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
838
+			interrupt-names = "gp",
839
+					  "gpmmu",
840
+					  "pp0",
841
+					  "ppmmu0",
842
+					  "pp1",
843
+					  "ppmmu1",
844
+					  "pmu";
845
+			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
846
+			clock-names = "bus", "core";
847
+			resets = <&ccu RST_BUS_GPU>;
530
848
 		};
531
849
 
532
850
 		gmac: ethernet@1c50000 {
..
..
@@ -546,6 +864,16 @@
546
864
 				#address-cells = <1>;
547
865
 				#size-cells = <0>;
548
866
 			};
867
+		};
868
+
869
+		mbus: dram-controller@1c62000 {
870
+			compatible = "allwinner,sun8i-r40-mbus";
871
+			reg = <0x01c62000 0x1000>;
872
+			clocks = <&ccu 155>;
873
+			#address-cells = <1>;
874
+			#size-cells = <1>;
875
+			dma-ranges = <0x00000000 0x40000000 0x80000000>;
876
+			#interconnect-cells = <1>;
549
877
 		};
550
878
 
551
879
 		tcon_top: tcon-top@1c70000 {
..
..
@@ -574,12 +902,9 @@
574
902
 				#size-cells = <0>;
575
903
 
576
904
 				tcon_top_mixer0_in: port@0 {
577
-					#address-cells = <1>;
578
-					#size-cells = <0>;
579
905
 					reg = <0>;
580
906
 
581
-					tcon_top_mixer0_in_mixer0: endpoint@0 {
582
-						reg = <0>;
907
+					tcon_top_mixer0_in_mixer0: endpoint {
583
908
 						remote-endpoint = <&mixer0_out_tcon_top>;
584
909
 					};
585
910
 				};
..
..
@@ -673,7 +998,7 @@
673
998
 			compatible = "allwinner,sun8i-r40-tcon-tv";
674
999
 			reg = <0x01c73000 0x1000>;
675
1000
 			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
676
-			clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>;
1001
+			clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>;
677
1002
 			clock-names = "ahb", "tcon-ch1";
678
1003
 			resets = <&ccu RST_BUS_TCON_TV0>;
679
1004
 			reset-names = "lcd";
..
..
@@ -716,7 +1041,7 @@
716
1041
 			compatible = "allwinner,sun8i-r40-tcon-tv";
717
1042
 			reg = <0x01c74000 0x1000>;
718
1043
 			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
719
-			clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>;
1044
+			clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>;
720
1045
 			clock-names = "ahb", "tcon-ch1";
721
1046
 			resets = <&ccu RST_BUS_TCON_TV1>;
722
1047
 			reset-names = "lcd";
..
..
@@ -758,7 +1083,7 @@
758
1083
 		gic: interrupt-controller@1c81000 {
759
1084
 			compatible = "arm,gic-400";
760
1085
 			reg = <0x01c81000 0x1000>,
761
-			      <0x01c82000 0x1000>,
1086
+			      <0x01c82000 0x2000>,
762
1087
 			      <0x01c84000 0x2000>,
763
1088
 			      <0x01c86000 0x2000>;
764
1089
 			interrupt-controller;
..
..
@@ -778,7 +1103,7 @@
778
1103
 			resets = <&ccu RST_BUS_HDMI1>;
779
1104
 			reset-names = "ctrl";
780
1105
 			phys = <&hdmi_phy>;
781
-			phy-names = "hdmi-phy";
1106
+			phy-names = "phy";
782
1107
 			status = "disabled";
783
1108
 
784
1109
 			ports {
..
..
@@ -803,7 +1128,7 @@
803
1128
 			compatible = "allwinner,sun8i-r40-hdmi-phy";
804
1129
 			reg = <0x01ef0000 0x10000>;
805
1130
 			clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>,
806
-				 <&ccu 7>, <&ccu 16>;
1131
+				 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>;
807
1132
 			clock-names = "bus", "mod", "pll-0", "pll-1";
808
1133
 			resets = <&ccu RST_BUS_HDMI0>;
809
1134
 			reset-names = "phy";
..
..
@@ -811,6 +1136,15 @@
811
1136
 		};
812
1137
 	};
813
1138
 
1139
+	pmu {
1140
+		compatible = "arm,cortex-a7-pmu";
1141
+		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1142
+			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1143
+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1144
+			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1145
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
1146
+	};
1147
+
814
1148
 	timer {
815
1149
 		compatible = "arm,armv7-timer";
816
1150
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,