add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/sun8i-h3.dtsi
..
..
@@ -41,9 +41,10 @@
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  */
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 #include "sunxi-h3-h5.dtsi"
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+#include <dt-bindings/thermal/thermal.h>
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 / {
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-	cpu0_opp_table: opp_table0 {
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+	cpu0_opp_table: opp-table-cpu {
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 		compatible = "operating-points-v2";
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 		opp-shared;
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..
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@@ -111,6 +112,26 @@
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 		};
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 	};
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+	gpu_opp_table: opp-table-gpu {
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+		compatible = "operating-points-v2";
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+
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+		opp-120000000 {
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+			opp-hz = /bits/ 64 <120000000>;
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+		};
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+
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+		opp-312000000 {
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+			opp-hz = /bits/ 64 <312000000>;
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+		};
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+
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+		opp-432000000 {
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+			opp-hz = /bits/ 64 <432000000>;
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+		};
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+
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+		opp-576000000 {
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+			opp-hz = /bits/ 64 <576000000>;
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+		};
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+	};
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+
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 	pmu {
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 		compatible = "arm,cortex-a7-pmu";
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 		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
..
..
@@ -129,7 +150,20 @@
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 	};
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 	soc {
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-		system-control@1c00000 {
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+		deinterlace: deinterlace@1400000 {
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+			compatible = "allwinner,sun8i-h3-deinterlace";
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+			reg = <0x01400000 0x20000>;
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+			clocks = <&ccu CLK_BUS_DEINTERLACE>,
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+				 <&ccu CLK_DEINTERLACE>,
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+				 <&ccu CLK_DRAM_DEINTERLACE>;
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+			clock-names = "bus", "mod", "ram";
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+			resets = <&ccu RST_BUS_DEINTERLACE>;
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+			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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+			interconnects = <&mbus 9>;
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+			interconnect-names = "dma-mem";
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+		};
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+
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+		syscon: system-control@1c00000 {
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 			compatible = "allwinner,sun8i-h3-system-control";
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 			reg = <0x01c00000 0x1000>;
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 			#address-cells = <1>;
..
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@@ -149,6 +183,26 @@
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 					reg = <0x000000 0x80000>;
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 				};
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 			};
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+		};
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+
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+		video-codec@1c0e000 {
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+			compatible = "allwinner,sun8i-h3-video-engine";
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+			reg = <0x01c0e000 0x1000>;
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+			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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+				 <&ccu CLK_DRAM_VE>;
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+			clock-names = "ahb", "mod", "ram";
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+			resets = <&ccu RST_BUS_VE>;
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+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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+			allwinner,sram = <&ve_sram 1>;
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+		};
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+
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+		crypto: crypto@1c15000 {
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+			compatible = "allwinner,sun8i-h3-crypto";
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+			reg = <0x01c15000 0x1000>;
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+			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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+			clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
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+			clock-names = "bus", "mod";
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+			resets = <&ccu RST_BUS_CE>;
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 		};
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 		mali: gpu@1c40000 {
..
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@@ -171,9 +225,51 @@
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 			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
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 			clock-names = "bus", "core";
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 			resets = <&ccu RST_BUS_GPU>;
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+			operating-points-v2 = <&gpu_opp_table>;
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+		};
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-			assigned-clocks = <&ccu CLK_GPU>;
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-			assigned-clock-rates = <384000000>;
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+		ths: thermal-sensor@1c25000 {
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+			compatible = "allwinner,sun8i-h3-ths";
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+			reg = <0x01c25000 0x400>;
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+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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+			resets = <&ccu RST_BUS_THS>;
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+			clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
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+			clock-names = "bus", "mod";
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+			nvmem-cells = <&ths_calibration>;
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+			nvmem-cell-names = "calibration";
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+			#thermal-sensor-cells = <0>;
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+		};
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+	};
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+
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+	thermal-zones {
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+		cpu_thermal: cpu-thermal {
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+			polling-delay-passive = <0>;
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+			polling-delay = <0>;
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+			thermal-sensors = <&ths 0>;
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+
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+			trips {
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+				cpu_hot_trip: cpu-hot {
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+					temperature = <80000>;
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+					hysteresis = <2000>;
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+					type = "passive";
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+				};
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+
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+				cpu_very_hot_trip: cpu-very-hot {
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+					temperature = <100000>;
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+					hysteresis = <0>;
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+					type = "critical";
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+				};
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+			};
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+
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+			cooling-maps {
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+				cpu-hot-limit {
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+					trip = <&cpu_hot_trip>;
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+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+				};
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+			};
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 		};
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 	};
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 };
..
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@@ -225,3 +321,11 @@
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 &pio {
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 	compatible = "allwinner,sun8i-h3-pinctrl";
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 };
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+
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+&rtc {
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+	compatible = "allwinner,sun8i-h3-rtc";
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+};
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+
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+&sid {
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+	compatible = "allwinner,sun8i-h3-sid";
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+};