add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/sun8i-a83t.dtsi
..
..
@@ -50,6 +50,7 @@
50
50
 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51
51
 #include <dt-bindings/reset/sun8i-de2.h>
52
52
 #include <dt-bindings/reset/sun8i-r-ccu.h>
53
+#include <dt-bindings/thermal/thermal.h>
53
54
 
54
55
 / {
55
56
 	interrupt-parent = <&gic>;
..
..
@@ -61,79 +62,91 @@
61
62
 		#size-cells = <0>;
62
63
 
63
64
 		cpu0: cpu@0 {
64
-			clocks = <&ccu CLK_C0CPUX>;
65
-			clock-names = "cpu";
66
65
 			compatible = "arm,cortex-a7";
67
66
 			device_type = "cpu";
67
+			clocks = <&ccu CLK_C0CPUX>;
68
68
 			operating-points-v2 = <&cpu0_opp_table>;
69
69
 			cci-control-port = <&cci_control0>;
70
70
 			enable-method = "allwinner,sun8i-a83t-smp";
71
71
 			reg = <0>;
72
+			#cooling-cells = <2>;
72
73
 		};
73
74
 
74
-		cpu@1 {
75
+		cpu1: cpu@1 {
75
76
 			compatible = "arm,cortex-a7";
76
77
 			device_type = "cpu";
78
+			clocks = <&ccu CLK_C0CPUX>;
77
79
 			operating-points-v2 = <&cpu0_opp_table>;
78
80
 			cci-control-port = <&cci_control0>;
79
81
 			enable-method = "allwinner,sun8i-a83t-smp";
80
82
 			reg = <1>;
83
+			#cooling-cells = <2>;
81
84
 		};
82
85
 
83
-		cpu@2 {
86
+		cpu2: cpu@2 {
84
87
 			compatible = "arm,cortex-a7";
85
88
 			device_type = "cpu";
89
+			clocks = <&ccu CLK_C0CPUX>;
86
90
 			operating-points-v2 = <&cpu0_opp_table>;
87
91
 			cci-control-port = <&cci_control0>;
88
92
 			enable-method = "allwinner,sun8i-a83t-smp";
89
93
 			reg = <2>;
94
+			#cooling-cells = <2>;
90
95
 		};
91
96
 
92
-		cpu@3 {
97
+		cpu3: cpu@3 {
93
98
 			compatible = "arm,cortex-a7";
94
99
 			device_type = "cpu";
100
+			clocks = <&ccu CLK_C0CPUX>;
95
101
 			operating-points-v2 = <&cpu0_opp_table>;
96
102
 			cci-control-port = <&cci_control0>;
97
103
 			enable-method = "allwinner,sun8i-a83t-smp";
98
104
 			reg = <3>;
105
+			#cooling-cells = <2>;
99
106
 		};
100
107
 
101
108
 		cpu100: cpu@100 {
102
-			clocks = <&ccu CLK_C1CPUX>;
103
-			clock-names = "cpu";
104
109
 			compatible = "arm,cortex-a7";
105
110
 			device_type = "cpu";
111
+			clocks = <&ccu CLK_C1CPUX>;
106
112
 			operating-points-v2 = <&cpu1_opp_table>;
107
113
 			cci-control-port = <&cci_control1>;
108
114
 			enable-method = "allwinner,sun8i-a83t-smp";
109
115
 			reg = <0x100>;
116
+			#cooling-cells = <2>;
110
117
 		};
111
118
 
112
-		cpu@101 {
119
+		cpu101: cpu@101 {
113
120
 			compatible = "arm,cortex-a7";
114
121
 			device_type = "cpu";
122
+			clocks = <&ccu CLK_C1CPUX>;
115
123
 			operating-points-v2 = <&cpu1_opp_table>;
116
124
 			cci-control-port = <&cci_control1>;
117
125
 			enable-method = "allwinner,sun8i-a83t-smp";
118
126
 			reg = <0x101>;
127
+			#cooling-cells = <2>;
119
128
 		};
120
129
 
121
-		cpu@102 {
130
+		cpu102: cpu@102 {
122
131
 			compatible = "arm,cortex-a7";
123
132
 			device_type = "cpu";
133
+			clocks = <&ccu CLK_C1CPUX>;
124
134
 			operating-points-v2 = <&cpu1_opp_table>;
125
135
 			cci-control-port = <&cci_control1>;
126
136
 			enable-method = "allwinner,sun8i-a83t-smp";
127
137
 			reg = <0x102>;
138
+			#cooling-cells = <2>;
128
139
 		};
129
140
 
130
-		cpu@103 {
141
+		cpu103: cpu@103 {
131
142
 			compatible = "arm,cortex-a7";
132
143
 			device_type = "cpu";
144
+			clocks = <&ccu CLK_C1CPUX>;
133
145
 			operating-points-v2 = <&cpu1_opp_table>;
134
146
 			cci-control-port = <&cci_control1>;
135
147
 			enable-method = "allwinner,sun8i-a83t-smp";
136
148
 			reg = <0x103>;
149
+			#cooling-cells = <2>;
137
150
 		};
138
151
 	};
139
152
 
..
..
@@ -187,12 +200,7 @@
187
200
 		status = "disabled";
188
201
 	};
189
202
 
190
-	memory {
191
-		reg = <0x40000000 0x80000000>;
192
-		device_type = "memory";
193
-	};
194
-
195
-	cpu0_opp_table: opp_table0 {
203
+	cpu0_opp_table: opp-table-cluster0 {
196
204
 		compatible = "operating-points-v2";
197
205
 		opp-shared;
198
206
 
..
..
@@ -245,7 +253,7 @@
245
253
 		};
246
254
 	};
247
255
 
248
-	cpu1_opp_table: opp_table1 {
256
+	cpu1_opp_table: opp-table-cluster1 {
249
257
 		compatible = "operating-points-v2";
250
258
 		opp-shared;
251
259
 
..
..
@@ -306,14 +314,25 @@
306
314
 
307
315
 		display_clocks: clock@1000000 {
308
316
 			compatible = "allwinner,sun8i-a83t-de2-clk";
309
-			reg = <0x01000000 0x100000>;
310
-			clocks = <&ccu CLK_PLL_DE>,
311
-				 <&ccu CLK_BUS_DE>;
312
-			clock-names = "mod",
313
-				      "bus";
317
+			reg = <0x01000000 0x10000>;
318
+			clocks = <&ccu CLK_BUS_DE>,
319
+				 <&ccu CLK_PLL_DE>;
320
+			clock-names = "bus",
321
+				      "mod";
314
322
 			resets = <&ccu RST_BUS_DE>;
315
323
 			#clock-cells = <1>;
316
324
 			#reset-cells = <1>;
325
+		};
326
+
327
+		rotate: rotate@1020000 {
328
+			compatible = "allwinner,sun8i-a83t-de2-rotate";
329
+			reg = <0x1020000 0x10000>;
330
+			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
331
+			clocks = <&display_clocks CLK_BUS_ROT>,
332
+				 <&display_clocks CLK_ROT>;
333
+			clock-names = "bus",
334
+				      "mod";
335
+			resets = <&display_clocks RST_ROT>;
317
336
 		};
318
337
 
319
338
 		mixer0: mixer@1100000 {
..
..
@@ -338,6 +357,11 @@
338
357
 						reg = <0>;
339
358
 						remote-endpoint = <&tcon0_in_mixer0>;
340
359
 					};
360
+
361
+					mixer0_out_tcon1: endpoint@1 {
362
+						reg = <1>;
363
+						remote-endpoint = <&tcon1_in_mixer0>;
364
+					};
341
365
 				};
342
366
 			};
343
367
 		};
..
..
@@ -356,9 +380,17 @@
356
380
 				#size-cells = <0>;
357
381
 
358
382
 				mixer1_out: port@1 {
383
+					#address-cells = <1>;
384
+					#size-cells = <0>;
359
385
 					reg = <1>;
360
386
 
361
-					mixer1_out_tcon1: endpoint {
387
+					mixer1_out_tcon0: endpoint@0 {
388
+						reg = <0>;
389
+						remote-endpoint = <&tcon0_in_mixer1>;
390
+					};
391
+
392
+					mixer1_out_tcon1: endpoint@1 {
393
+						reg = <1>;
362
394
 						remote-endpoint = <&tcon1_in_mixer1>;
363
395
 					};
364
396
 				};
..
..
@@ -425,6 +457,7 @@
425
457
 			clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
426
458
 			clock-names = "ahb", "tcon-ch0";
427
459
 			clock-output-names = "tcon-pixel-clock";
460
+			#clock-cells = <0>;
428
461
 			resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
429
462
 			reset-names = "lcd", "lvds";
430
463
 
..
..
@@ -441,11 +474,14 @@
441
474
 						reg = <0>;
442
475
 						remote-endpoint = <&mixer0_out_tcon0>;
443
476
 					};
477
+
478
+					tcon0_in_mixer1: endpoint@1 {
479
+						reg = <1>;
480
+						remote-endpoint = <&mixer1_out_tcon0>;
481
+					};
444
482
 				};
445
483
 
446
484
 				tcon0_out: port@1 {
447
-					#address-cells = <1>;
448
-					#size-cells = <0>;
449
485
 					reg = <1>;
450
486
 				};
451
487
 			};
..
..
@@ -465,9 +501,17 @@
465
501
 				#size-cells = <0>;
466
502
 
467
503
 				tcon1_in: port@0 {
504
+					#address-cells = <1>;
505
+					#size-cells = <0>;
468
506
 					reg = <0>;
469
507
 
470
-					tcon1_in_mixer1: endpoint {
508
+					tcon1_in_mixer0: endpoint@0 {
509
+						reg = <0>;
510
+						remote-endpoint = <&mixer0_out_tcon1>;
511
+					};
512
+
513
+					tcon1_in_mixer1: endpoint@1 {
514
+						reg = <1>;
471
515
 						remote-endpoint = <&mixer1_out_tcon1>;
472
516
 					};
473
517
 				};
..
..
@@ -549,6 +593,31 @@
549
593
 		sid: eeprom@1c14000 {
550
594
 			compatible = "allwinner,sun8i-a83t-sid";
551
595
 			reg = <0x1c14000 0x400>;
596
+			#address-cells = <1>;
597
+			#size-cells = <1>;
598
+
599
+			ths_calibration: thermal-sensor-calibration@34 {
600
+				reg = <0x34 8>;
601
+			};
602
+		};
603
+
604
+		crypto: crypto@1c15000 {
605
+			compatible = "allwinner,sun8i-a83t-crypto";
606
+			reg = <0x01c15000 0x1000>;
607
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
608
+			resets = <&ccu RST_BUS_SS>;
609
+			clocks = <&ccu CLK_BUS_SS>, <&ccu CLK_SS>;
610
+			clock-names = "bus", "mod";
611
+		};
612
+
613
+		msgbox: mailbox@1c17000 {
614
+			compatible = "allwinner,sun8i-a83t-msgbox",
615
+				     "allwinner,sun6i-a31-msgbox";
616
+			reg = <0x01c17000 0x1000>;
617
+			clocks = <&ccu CLK_BUS_MSGBOX>;
618
+			resets = <&ccu RST_BUS_MSGBOX>;
619
+			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
620
+			#mbox-cells = <1>;
552
621
 		};
553
622
 
554
623
 		usb_otg: usb@1c19000 {
..
..
@@ -562,6 +631,7 @@
562
631
 			phys = <&usbphy 0>;
563
632
 			phy-names = "usb";
564
633
 			extcon = <&usbphy 0>;
634
+			dr_mode = "otg";
565
635
 			status = "disabled";
566
636
 		};
567
637
 
..
..
@@ -649,6 +719,20 @@
649
719
 			#interrupt-cells = <3>;
650
720
 			#gpio-cells = <3>;
651
721
 
722
+			/omit-if-no-ref/
723
+			csi_8bit_parallel_pins: csi-8bit-parallel-pins {
724
+				pins = "PE0", "PE2", "PE3", "PE6", "PE7",
725
+				       "PE8", "PE9", "PE10", "PE11",
726
+				       "PE12", "PE13";
727
+				function = "csi";
728
+			};
729
+
730
+			/omit-if-no-ref/
731
+			csi_mclk_pin: csi-mclk-pin {
732
+				pins = "PE1";
733
+				function = "csi";
734
+			};
735
+
652
736
 			emac_rgmii_pins: emac-rgmii-pins {
653
737
 				pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
654
738
 				       "PD11", "PD12", "PD13", "PD14", "PD18",
..
..
@@ -674,6 +758,12 @@
674
758
 			i2c1_pins: i2c1-pins {
675
759
 				pins = "PH2", "PH3";
676
760
 				function = "i2c1";
761
+			};
762
+
763
+			/omit-if-no-ref/
764
+			i2c2_pe_pins: i2c2-pe-pins {
765
+				pins = "PE14", "PE15";
766
+				function = "i2c2";
677
767
 			};
678
768
 
679
769
 			i2c2_ph_pins: i2c2-ph-pins {
..
..
@@ -747,10 +837,16 @@
747
837
 				pins = "PG8", "PG9";
748
838
 				function = "uart1";
749
839
 			};
840
+
841
+			/omit-if-no-ref/
842
+			uart2_pb_pins: uart2-pb-pins {
843
+				pins = "PB0", "PB1";
844
+				function = "uart2";
845
+			};
750
846
 		};
751
847
 
752
848
 		timer@1c20c00 {
753
-			compatible = "allwinner,sun4i-a10-timer";
849
+			compatible = "allwinner,sun8i-a23-timer";
754
850
 			reg = <0x01c20c00 0xa0>;
755
851
 			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
756
852
 				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -852,6 +948,39 @@
852
948
 			status = "disabled";
853
949
 		};
854
950
 
951
+		uart2: serial@1c28800 {
952
+			compatible = "snps,dw-apb-uart";
953
+			reg = <0x01c28800 0x400>;
954
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
955
+			reg-shift = <2>;
956
+			reg-io-width = <4>;
957
+			clocks = <&ccu CLK_BUS_UART2>;
958
+			resets = <&ccu RST_BUS_UART2>;
959
+			status = "disabled";
960
+		};
961
+
962
+		uart3: serial@1c28c00 {
963
+			compatible = "snps,dw-apb-uart";
964
+			reg = <0x01c28c00 0x400>;
965
+			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
966
+			reg-shift = <2>;
967
+			reg-io-width = <4>;
968
+			clocks = <&ccu CLK_BUS_UART3>;
969
+			resets = <&ccu RST_BUS_UART3>;
970
+			status = "disabled";
971
+		};
972
+
973
+		uart4: serial@1c29000 {
974
+			compatible = "snps,dw-apb-uart";
975
+			reg = <0x01c29000 0x400>;
976
+			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
977
+			reg-shift = <2>;
978
+			reg-io-width = <4>;
979
+			clocks = <&ccu CLK_BUS_UART4>;
980
+			resets = <&ccu RST_BUS_UART4>;
981
+			status = "disabled";
982
+		};
983
+
855
984
 		i2c0: i2c@1c2ac00 {
856
985
 			compatible = "allwinner,sun8i-a83t-i2c",
857
986
 				     "allwinner,sun6i-a31-i2c";
..
..
@@ -898,10 +1027,10 @@
898
1027
 			reg = <0x01c30000 0x104>;
899
1028
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
900
1029
 			interrupt-names = "macirq";
901
-			resets = <&ccu 13>;
902
-			reset-names = "stmmaceth";
903
-			clocks = <&ccu 27>;
1030
+			clocks = <&ccu CLK_BUS_EMAC>;
904
1031
 			clock-names = "stmmaceth";
1032
+			resets = <&ccu RST_BUS_EMAC>;
1033
+			reset-names = "stmmaceth";
905
1034
 			status = "disabled";
906
1035
 
907
1036
 			mdio: mdio {
..
..
@@ -912,7 +1041,7 @@
912
1041
 		};
913
1042
 
914
1043
 		gic: interrupt-controller@1c81000 {
915
-			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1044
+			compatible = "arm,gic-400";
916
1045
 			reg = <0x01c81000 0x1000>,
917
1046
 			      <0x01c82000 0x2000>,
918
1047
 			      <0x01c84000 0x2000>,
..
..
@@ -920,6 +1049,21 @@
920
1049
 			interrupt-controller;
921
1050
 			#interrupt-cells = <3>;
922
1051
 			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1052
+		};
1053
+
1054
+		csi: camera@1cb0000 {
1055
+			compatible = "allwinner,sun8i-a83t-csi";
1056
+			reg = <0x01cb0000 0x1000>;
1057
+			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1058
+			clocks = <&ccu CLK_BUS_CSI>,
1059
+				 <&ccu CLK_CSI_SCLK>,
1060
+				 <&ccu CLK_DRAM_CSI>;
1061
+			clock-names = "bus", "mod", "ram";
1062
+			resets = <&ccu RST_BUS_CSI>;
1063
+			status = "disabled";
1064
+
1065
+			csi_in: port {
1066
+			};
923
1067
 		};
924
1068
 
925
1069
 		hdmi: hdmi@1ee0000 {
..
..
@@ -933,7 +1077,7 @@
933
1077
 			resets = <&ccu RST_BUS_HDMI1>;
934
1078
 			reset-names = "ctrl";
935
1079
 			phys = <&hdmi_phy>;
936
-			phy-names = "hdmi-phy";
1080
+			phy-names = "phy";
937
1081
 			pinctrl-names = "default";
938
1082
 			pinctrl-0 = <&hdmi_pins>;
939
1083
 			status = "disabled";
..
..
@@ -979,7 +1123,7 @@
979
1123
 			compatible = "allwinner,sun8i-a83t-r-ccu";
980
1124
 			reg = <0x01f01400 0x400>;
981
1125
 			clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
982
-				 <&ccu 6>;
1126
+				 <&ccu CLK_PLL_PERIPH>;
983
1127
 			clock-names = "hosc", "losc", "iosc", "pll-periph";
984
1128
 			#clock-cells = <1>;
985
1129
 			#reset-cells = <1>;
..
..
@@ -988,6 +1132,26 @@
988
1132
 		r_cpucfg@1f01c00 {
989
1133
 			compatible = "allwinner,sun8i-a83t-r-cpucfg";
990
1134
 			reg = <0x1f01c00 0x400>;
1135
+		};
1136
+
1137
+		r_cir: ir@1f02000 {
1138
+			compatible = "allwinner,sun8i-a83t-ir",
1139
+				"allwinner,sun6i-a31-ir";
1140
+			clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1141
+			clock-names = "apb", "ir";
1142
+			resets = <&r_ccu RST_APB0_IR>;
1143
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1144
+			reg = <0x01f02000 0x400>;
1145
+			pinctrl-names = "default";
1146
+			pinctrl-0 = <&r_cir_pin>;
1147
+			status = "disabled";
1148
+		};
1149
+
1150
+		r_lradc: lradc@1f03c00 {
1151
+			compatible = "allwinner,sun8i-a83t-r-lradc";
1152
+			reg = <0x01f03c00 0x100>;
1153
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1154
+			status = "disabled";
991
1155
 		};
992
1156
 
993
1157
 		r_pio: pinctrl@1f02c00 {
..
..
@@ -1001,6 +1165,11 @@
1001
1165
 			#gpio-cells = <3>;
1002
1166
 			interrupt-controller;
1003
1167
 			#interrupt-cells = <3>;
1168
+
1169
+			r_cir_pin: r-cir-pin {
1170
+				pins = "PL12";
1171
+				function = "s_cir_rx";
1172
+			};
1004
1173
 
1005
1174
 			r_rsb_pins: r-rsb-pins {
1006
1175
 				pins = "PL0", "PL1";
..
..
@@ -1024,5 +1193,82 @@
1024
1193
 			#address-cells = <1>;
1025
1194
 			#size-cells = <0>;
1026
1195
 		};
1196
+
1197
+		ths: thermal-sensor@1f04000 {
1198
+			compatible = "allwinner,sun8i-a83t-ths";
1199
+			reg = <0x01f04000 0x100>;
1200
+			interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1201
+			nvmem-cells = <&ths_calibration>;
1202
+			nvmem-cell-names = "calibration";
1203
+			#thermal-sensor-cells = <1>;
1204
+		};
1205
+	};
1206
+
1207
+	thermal-zones {
1208
+		cpu0_thermal: cpu0-thermal {
1209
+			polling-delay-passive = <0>;
1210
+			polling-delay = <0>;
1211
+			thermal-sensors = <&ths 0>;
1212
+
1213
+			trips {
1214
+				cpu0_hot: cpu-hot {
1215
+					temperature = <80000>;
1216
+					hysteresis = <2000>;
1217
+					type = "passive";
1218
+				};
1219
+
1220
+				cpu0_very_hot: cpu-very-hot {
1221
+					temperature = <100000>;
1222
+					hysteresis = <0>;
1223
+					type = "critical";
1224
+				};
1225
+			};
1226
+
1227
+			cooling-maps {
1228
+				cpu-hot-limit {
1229
+					trip = <&cpu0_hot>;
1230
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1231
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1232
+							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1233
+							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1234
+				};
1235
+			};
1236
+		};
1237
+
1238
+		cpu1_thermal: cpu1-thermal {
1239
+			polling-delay-passive = <0>;
1240
+			polling-delay = <0>;
1241
+			thermal-sensors = <&ths 1>;
1242
+
1243
+			trips {
1244
+				cpu1_hot: cpu-hot {
1245
+					temperature = <80000>;
1246
+					hysteresis = <2000>;
1247
+					type = "passive";
1248
+				};
1249
+
1250
+				cpu1_very_hot: cpu-very-hot {
1251
+					temperature = <100000>;
1252
+					hysteresis = <0>;
1253
+					type = "critical";
1254
+				};
1255
+			};
1256
+
1257
+			cooling-maps {
1258
+				cpu-hot-limit {
1259
+					trip = <&cpu1_hot>;
1260
+					cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1261
+							 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1262
+							 <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1263
+							 <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1264
+				};
1265
+			};
1266
+		};
1267
+
1268
+		gpu_thermal: gpu-thermal {
1269
+			polling-delay-passive = <0>;
1270
+			polling-delay = <0>;
1271
+			thermal-sensors = <&ths 2>;
1272
+		};
1027
1273
 	};
1028
1274
 };