forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/sun7i-a20.dtsi
....@@ -42,16 +42,17 @@
4242  *     OTHER DEALINGS IN THE SOFTWARE.
4343  */
4444 
45
-#include "skeleton.dtsi"
46
-
4745 #include <dt-bindings/interrupt-controller/arm-gic.h>
4846 #include <dt-bindings/thermal/thermal.h>
4947 #include <dt-bindings/dma/sun4i-a10.h>
5048 #include <dt-bindings/clock/sun7i-a20-ccu.h>
5149 #include <dt-bindings/reset/sun4i-a10-ccu.h>
50
+#include <dt-bindings/pinctrl/sun4i-a10.h>
5251 
5352 / {
5453 	interrupt-parent = <&gic>;
54
+	#address-cells = <1>;
55
+	#size-cells = <1>;
5556 
5657 	aliases {
5758 		ethernet0 = &gmac;
....@@ -62,7 +63,7 @@
6263 		#size-cells = <1>;
6364 		ranges;
6465 
65
-		framebuffer@0 {
66
+		framebuffer-lcd0-hdmi {
6667 			compatible = "allwinner,simple-framebuffer",
6768 				     "simple-framebuffer";
6869 			allwinner,pipeline = "de_be0-lcd0-hdmi";
....@@ -73,7 +74,7 @@
7374 			status = "disabled";
7475 		};
7576 
76
-		framebuffer@1 {
77
+		framebuffer-lcd0 {
7778 			compatible = "allwinner,simple-framebuffer",
7879 				     "simple-framebuffer";
7980 			allwinner,pipeline = "de_be0-lcd0";
....@@ -83,7 +84,7 @@
8384 			status = "disabled";
8485 		};
8586 
86
-		framebuffer@2 {
87
+		framebuffer-lcd0-tve0 {
8788 			compatible = "allwinner,simple-framebuffer",
8889 				     "simple-framebuffer";
8990 			allwinner,pipeline = "de_be0-lcd0-tve0";
....@@ -118,7 +119,7 @@
118119 			#cooling-cells = <2>;
119120 		};
120121 
121
-		cpu@1 {
122
+		cpu1: cpu@1 {
122123 			compatible = "arm,cortex-a7";
123124 			device_type = "cpu";
124125 			reg = <1>;
....@@ -148,7 +149,8 @@
148149 			cooling-maps {
149150 				map0 {
150151 					trip = <&cpu_alert0>;
151
-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
152
+					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
153
+							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
152154 				};
153155 			};
154156 
....@@ -170,8 +172,19 @@
170172 		};
171173 	};
172174 
173
-	memory {
174
-		reg = <0x40000000 0x80000000>;
175
+	reserved-memory {
176
+		#address-cells = <1>;
177
+		#size-cells = <1>;
178
+		ranges;
179
+
180
+		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
181
+		default-pool {
182
+			compatible = "shared-dma-pool";
183
+			size = <0x6000000>;
184
+			alloc-ranges = <0x40000000 0x10000000>;
185
+			reusable;
186
+			linux,cma-default;
187
+		};
175188 	};
176189 
177190 	timer {
....@@ -193,14 +206,14 @@
193206 		#size-cells = <1>;
194207 		ranges;
195208 
196
-		osc24M: clk@1c20050 {
209
+		osc24M: clk-24M {
197210 			#clock-cells = <0>;
198211 			compatible = "fixed-clock";
199212 			clock-frequency = <24000000>;
200213 			clock-output-names = "osc24M";
201214 		};
202215 
203
-		osc32k: clk@0 {
216
+		osc32k: clk-32k {
204217 			#clock-cells = <0>;
205218 			compatible = "fixed-clock";
206219 			clock-frequency = <32768>;
....@@ -216,14 +229,14 @@
216229 		 * The actual TX clock rate is not controlled by the
217230 		 * gmac_tx clock.
218231 		 */
219
-		mii_phy_tx_clk: clk@1 {
232
+		mii_phy_tx_clk: clk-mii-phy-tx {
220233 			#clock-cells = <0>;
221234 			compatible = "fixed-clock";
222235 			clock-frequency = <25000000>;
223236 			clock-output-names = "mii_phy_tx";
224237 		};
225238 
226
-		gmac_int_tx_clk: clk@2 {
239
+		gmac_int_tx_clk: clk-gmac-int-tx {
227240 			#clock-cells = <0>;
228241 			compatible = "fixed-clock";
229242 			clock-frequency = <125000000>;
....@@ -246,7 +259,7 @@
246259 		status = "disabled";
247260 	};
248261 
249
-	soc@1c00000 {
262
+	soc {
250263 		compatible = "simple-bus";
251264 		#address-cells = <1>;
252265 		#size-cells = <1>;
....@@ -321,7 +334,7 @@
321334 			#dma-cells = <2>;
322335 		};
323336 
324
-		nfc: nand@1c03000 {
337
+		nfc: nand-controller@1c03000 {
325338 			compatible = "allwinner,sun4i-a10-nand";
326339 			reg = <0x01c03000 0x1000>;
327340 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
....@@ -364,6 +377,16 @@
364377 			num-cs = <1>;
365378 		};
366379 
380
+		csi0: csi@1c09000 {
381
+			compatible = "allwinner,sun7i-a20-csi0";
382
+			reg = <0x01c09000 0x1000>;
383
+			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
384
+			clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
385
+			clock-names = "bus", "isp", "ram";
386
+			resets = <&ccu RST_CSI0>;
387
+			status = "disabled";
388
+		};
389
+
367390 		emac: ethernet@1c0b000 {
368391 			compatible = "allwinner,sun4i-a10-emac";
369392 			reg = <0x01c0b000 0x1000>;
....@@ -382,11 +405,12 @@
382405 		};
383406 
384407 		tcon0: lcd-controller@1c0c000 {
385
-			compatible = "allwinner,sun7i-a20-tcon";
408
+			compatible = "allwinner,sun7i-a20-tcon0",
409
+				     "allwinner,sun7i-a20-tcon";
386410 			reg = <0x01c0c000 0x1000>;
387411 			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
388
-			resets = <&ccu RST_TCON0>;
389
-			reset-names = "lcd";
412
+			resets = <&ccu RST_TCON0>, <&ccu RST_LVDS>;
413
+			reset-names = "lcd", "lvds";
390414 			clocks = <&ccu CLK_AHB_LCD0>,
391415 				 <&ccu CLK_TCON0_CH0>,
392416 				 <&ccu CLK_TCON0_CH1>;
....@@ -394,6 +418,7 @@
394418 				      "tcon-ch0",
395419 				      "tcon-ch1";
396420 			clock-output-names = "tcon0-pixel-clock";
421
+			#clock-cells = <0>;
397422 			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
398423 
399424 			ports {
....@@ -431,7 +456,8 @@
431456 		};
432457 
433458 		tcon1: lcd-controller@1c0d000 {
434
-			compatible = "allwinner,sun7i-a20-tcon";
459
+			compatible = "allwinner,sun7i-a20-tcon1",
460
+				     "allwinner,sun7i-a20-tcon";
435461 			reg = <0x01c0d000 0x1000>;
436462 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
437463 			resets = <&ccu RST_TCON1>;
....@@ -443,6 +469,7 @@
443469 				      "tcon-ch0",
444470 				      "tcon-ch1";
445471 			clock-output-names = "tcon1-pixel-clock";
472
+			#clock-cells = <0>;
446473 			dmas = <&dma SUN4I_DMA_DEDICATED 15>;
447474 
448475 			ports {
....@@ -479,6 +506,17 @@
479506 			};
480507 		};
481508 
509
+		video-codec@1c0e000 {
510
+			compatible = "allwinner,sun7i-a20-video-engine";
511
+			reg = <0x01c0e000 0x1000>;
512
+			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
513
+				 <&ccu CLK_DRAM_VE>;
514
+			clock-names = "ahb", "mod", "ram";
515
+			resets = <&ccu RST_VE>;
516
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
517
+			allwinner,sram = <&ve_sram 1>;
518
+		};
519
+
482520 		mmc0: mmc@1c0f000 {
483521 			compatible = "allwinner,sun7i-a20-mmc";
484522 			reg = <0x01c0f000 0x1000>;
....@@ -491,6 +529,8 @@
491529 				      "output",
492530 				      "sample";
493531 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
532
+			pinctrl-names = "default";
533
+			pinctrl-0 = <&mmc0_pins>;
494534 			status = "disabled";
495535 			#address-cells = <1>;
496536 			#size-cells = <0>;
....@@ -525,6 +565,8 @@
525565 				      "output",
526566 				      "sample";
527567 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
568
+			pinctrl-names = "default";
569
+			pinctrl-0 = <&mmc2_pins>;
528570 			status = "disabled";
529571 			#address-cells = <1>;
530572 			#size-cells = <0>;
....@@ -542,6 +584,8 @@
542584 				      "output",
543585 				      "sample";
544586 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
587
+			pinctrl-names = "default";
588
+			pinctrl-0 = <&mmc3_pins>;
545589 			status = "disabled";
546590 			#address-cells = <1>;
547591 			#size-cells = <0>;
....@@ -557,13 +601,14 @@
557601 			phy-names = "usb";
558602 			extcon = <&usbphy 0>;
559603 			allwinner,sram = <&otg_sram 1>;
604
+			dr_mode = "otg";
560605 			status = "disabled";
561606 		};
562607 
563608 		usbphy: phy@1c13400 {
564609 			#phy-cells = <1>;
565610 			compatible = "allwinner,sun7i-a20-usb-phy";
566
-			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
611
+			reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
567612 			reg-names = "phy_ctrl", "pmu1", "pmu2";
568613 			clocks = <&ccu CLK_USB_PHY>;
569614 			clock-names = "usb_phy";
....@@ -687,6 +732,17 @@
687732 			status = "disabled";
688733 		};
689734 
735
+		csi1: csi@1c1d000 {
736
+			compatible = "allwinner,sun7i-a20-csi1",
737
+				     "allwinner,sun4i-a10-csi1";
738
+			reg = <0x01c1d000 0x1000>;
739
+			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
740
+			clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
741
+			clock-names = "bus", "ram";
742
+			resets = <&ccu RST_CSI1>;
743
+			status = "disabled";
744
+		};
745
+
690746 		spi3: spi@1c1f000 {
691747 			compatible = "allwinner,sun4i-a10-spi";
692748 			reg = <0x01c1f000 0x1000>;
....@@ -722,22 +778,71 @@
722778 			#interrupt-cells = <3>;
723779 			#gpio-cells = <3>;
724780 
725
-			can0_pins_a: can0@0 {
781
+			/omit-if-no-ref/
782
+			can_pa_pins: can-pa-pins {
783
+				pins = "PA16", "PA17";
784
+				function = "can";
785
+			};
786
+
787
+			/omit-if-no-ref/
788
+			can_ph_pins: can-ph-pins {
726789 				pins = "PH20", "PH21";
727790 				function = "can";
728791 			};
729792 
730
-			clk_out_a_pins_a: clk_out_a@0 {
793
+			/omit-if-no-ref/
794
+			clk_out_a_pin: clk-out-a-pin {
731795 				pins = "PI12";
732796 				function = "clk_out_a";
733797 			};
734798 
735
-			clk_out_b_pins_a: clk_out_b@0 {
799
+			/omit-if-no-ref/
800
+			clk_out_b_pin: clk-out-b-pin {
736801 				pins = "PI13";
737802 				function = "clk_out_b";
738803 			};
739804 
740
-			emac_pins_a: emac0@0 {
805
+			/omit-if-no-ref/
806
+			csi0_8bits_pins: csi-8bits-pins {
807
+				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
808
+				       "PE6", "PE7", "PE8", "PE9", "PE10",
809
+				       "PE11";
810
+				function = "csi0";
811
+			};
812
+
813
+			/omit-if-no-ref/
814
+			csi0_clk_pin: csi-clk-pin {
815
+				pins = "PE1";
816
+				function = "csi0";
817
+			};
818
+
819
+			/omit-if-no-ref/
820
+			csi1_8bits_pg_pins: csi1-8bits-pg-pins {
821
+				pins = "PG0", "PG2", "PG3", "PG4", "PG5",
822
+				       "PG6", "PG7", "PG8", "PG9", "PG10",
823
+				       "PG11";
824
+				function = "csi1";
825
+			};
826
+
827
+			/omit-if-no-ref/
828
+			csi1_24bits_ph_pins: csi1-24bits-ph-pins {
829
+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",
830
+				       "PH5", "PH6", "PH7", "PH8", "PH9",
831
+				       "PH10", "PH11", "PH12", "PH13", "PH14",
832
+				       "PH15", "PH16", "PH17", "PH18", "PH19",
833
+				       "PH20", "PH21", "PH22", "PH23", "PH24",
834
+				       "PH25", "PH26", "PH27";
835
+				function = "csi1";
836
+			};
837
+
838
+			/omit-if-no-ref/
839
+			csi1_clk_pg_pin: csi1-clk-pg-pin {
840
+				pins = "PG1";
841
+				function = "csi1";
842
+			};
843
+
844
+			/omit-if-no-ref/
845
+			emac_pa_pins: emac-pa-pins {
741846 				pins = "PA0", "PA1", "PA2",
742847 				       "PA3", "PA4", "PA5", "PA6",
743848 				       "PA7", "PA8", "PA9", "PA10",
....@@ -746,7 +851,18 @@
746851 				function = "emac";
747852 			};
748853 
749
-			gmac_pins_mii_a: gmac_mii@0 {
854
+			/omit-if-no-ref/
855
+			emac_ph_pins: emac-ph-pins {
856
+				pins = "PH8", "PH9", "PH10", "PH11",
857
+				       "PH14", "PH15", "PH16", "PH17",
858
+				       "PH18", "PH19", "PH20", "PH21",
859
+				       "PH22", "PH23", "PH24", "PH25",
860
+				       "PH26";
861
+				function = "emac";
862
+			};
863
+
864
+			/omit-if-no-ref/
865
+			gmac_mii_pins: gmac-mii-pins {
750866 				pins = "PA0", "PA1", "PA2",
751867 				       "PA3", "PA4", "PA5", "PA6",
752868 				       "PA7", "PA8", "PA9", "PA10",
....@@ -755,7 +871,8 @@
755871 				function = "gmac";
756872 			};
757873 
758
-			gmac_pins_rgmii_a: gmac_rgmii@0 {
874
+			/omit-if-no-ref/
875
+			gmac_rgmii_pins: gmac-rgmii-pins {
759876 				pins = "PA0", "PA1", "PA2",
760877 				       "PA3", "PA4", "PA5", "PA6",
761878 				        "PA7", "PA8", "PA10",
....@@ -769,47 +886,70 @@
769886 				drive-strength = <40>;
770887 			};
771888 
772
-			i2c0_pins_a: i2c0@0 {
889
+			/omit-if-no-ref/
890
+			i2c0_pins: i2c0-pins {
773891 				pins = "PB0", "PB1";
774892 				function = "i2c0";
775893 			};
776894 
777
-			i2c1_pins_a: i2c1@0 {
895
+			/omit-if-no-ref/
896
+			i2c1_pins: i2c1-pins {
778897 				pins = "PB18", "PB19";
779898 				function = "i2c1";
780899 			};
781900 
782
-			i2c2_pins_a: i2c2@0 {
901
+			/omit-if-no-ref/
902
+			i2c2_pins: i2c2-pins {
783903 				pins = "PB20", "PB21";
784904 				function = "i2c2";
785905 			};
786906 
787
-			i2c3_pins_a: i2c3@0 {
907
+			/omit-if-no-ref/
908
+			i2c3_pins: i2c3-pins {
788909 				pins = "PI0", "PI1";
789910 				function = "i2c3";
790911 			};
791912 
792
-			ir0_rx_pins_a: ir0@0 {
913
+			/omit-if-no-ref/
914
+			ir0_rx_pin: ir0-rx-pin {
793915 				pins = "PB4";
794916 				function = "ir0";
795917 			};
796918 
797
-			ir0_tx_pins_a: ir0@1 {
919
+			/omit-if-no-ref/
920
+			ir0_tx_pin: ir0-tx-pin {
798921 				pins = "PB3";
799922 				function = "ir0";
800923 			};
801924 
802
-			ir1_rx_pins_a: ir1@0 {
925
+			/omit-if-no-ref/
926
+			ir1_rx_pin: ir1-rx-pin {
803927 				pins = "PB23";
804928 				function = "ir1";
805929 			};
806930 
807
-			ir1_tx_pins_a: ir1@1 {
931
+			/omit-if-no-ref/
932
+			ir1_tx_pin: ir1-tx-pin {
808933 				pins = "PB22";
809934 				function = "ir1";
810935 			};
811936 
812
-			mmc0_pins_a: mmc0@0 {
937
+			/omit-if-no-ref/
938
+			lcd_lvds0_pins: lcd-lvds0-pins {
939
+				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
940
+				       "PD5", "PD6", "PD7", "PD8", "PD9";
941
+				function = "lvds0";
942
+			};
943
+
944
+			/omit-if-no-ref/
945
+			lcd_lvds1_pins: lcd-lvds1-pins {
946
+				pins = "PD10", "PD11", "PD12", "PD13", "PD14",
947
+				       "PD15", "PD16", "PD17", "PD18", "PD19";
948
+				function = "lvds1";
949
+			};
950
+
951
+			/omit-if-no-ref/
952
+			mmc0_pins: mmc0-pins {
813953 				pins = "PF0", "PF1", "PF2",
814954 				       "PF3", "PF4", "PF5";
815955 				function = "mmc0";
....@@ -817,7 +957,8 @@
817957 				bias-pull-up;
818958 			};
819959 
820
-			mmc2_pins_a: mmc2@0 {
960
+			/omit-if-no-ref/
961
+			mmc2_pins: mmc2-pins {
821962 				pins = "PC6", "PC7", "PC8",
822963 				       "PC9", "PC10", "PC11";
823964 				function = "mmc2";
....@@ -825,7 +966,8 @@
825966 				bias-pull-up;
826967 			};
827968 
828
-			mmc3_pins_a: mmc3@0 {
969
+			/omit-if-no-ref/
970
+			mmc3_pins: mmc3-pins {
829971 				pins = "PI4", "PI5", "PI6",
830972 				       "PI7", "PI8", "PI9";
831973 				function = "mmc3";
....@@ -833,118 +975,207 @@
833975 				bias-pull-up;
834976 			};
835977 
836
-			ps20_pins_a: ps20@0 {
978
+			/omit-if-no-ref/
979
+			ps2_0_pins: ps2-0-pins {
837980 				pins = "PI20", "PI21";
838981 				function = "ps2";
839982 			};
840983 
841
-			ps21_pins_a: ps21@0 {
984
+			/omit-if-no-ref/
985
+			ps2_1_ph_pins: ps2-1-ph-pins {
842986 				pins = "PH12", "PH13";
843987 				function = "ps2";
844988 			};
845989 
846
-			pwm0_pins_a: pwm0@0 {
990
+			/omit-if-no-ref/
991
+			pwm0_pin: pwm0-pin {
847992 				pins = "PB2";
848993 				function = "pwm";
849994 			};
850995 
851
-			pwm1_pins_a: pwm1@0 {
996
+			/omit-if-no-ref/
997
+			pwm1_pin: pwm1-pin {
852998 				pins = "PI3";
853999 				function = "pwm";
8541000 			};
8551001 
856
-			spdif_tx_pins_a: spdif@0 {
1002
+			/omit-if-no-ref/
1003
+			spdif_tx_pin: spdif-tx-pin {
8571004 				pins = "PB13";
8581005 				function = "spdif";
8591006 				bias-pull-up;
8601007 			};
8611008 
862
-			spi0_pins_a: spi0@0 {
1009
+			/omit-if-no-ref/
1010
+			spi0_pi_pins: spi0-pi-pins {
8631011 				pins = "PI11", "PI12", "PI13";
8641012 				function = "spi0";
8651013 			};
8661014 
867
-			spi0_cs0_pins_a: spi0_cs0@0 {
1015
+			/omit-if-no-ref/
1016
+			spi0_cs0_pi_pin: spi0-cs0-pi-pin {
8681017 				pins = "PI10";
8691018 				function = "spi0";
8701019 			};
8711020 
872
-			spi0_cs1_pins_a: spi0_cs1@0 {
1021
+			/omit-if-no-ref/
1022
+			spi0_cs1_pi_pin: spi0-cs1-pi-pin {
8731023 				pins = "PI14";
8741024 				function = "spi0";
8751025 			};
8761026 
877
-			spi1_pins_a: spi1@0 {
1027
+			/omit-if-no-ref/
1028
+			spi1_pi_pins: spi1-pi-pins {
8781029 				pins = "PI17", "PI18", "PI19";
8791030 				function = "spi1";
8801031 			};
8811032 
882
-			spi1_cs0_pins_a: spi1_cs0@0 {
1033
+			/omit-if-no-ref/
1034
+			spi1_cs0_pi_pin: spi1-cs0-pi-pin {
8831035 				pins = "PI16";
8841036 				function = "spi1";
8851037 			};
8861038 
887
-			spi2_pins_a: spi2@0 {
888
-				pins = "PC20", "PC21", "PC22";
889
-				function = "spi2";
890
-			};
891
-
892
-			spi2_pins_b: spi2@1 {
1039
+			/omit-if-no-ref/
1040
+			spi2_pb_pins: spi2-pb-pins {
8931041 				pins = "PB15", "PB16", "PB17";
8941042 				function = "spi2";
8951043 			};
8961044 
897
-			spi2_cs0_pins_a: spi2_cs0@0 {
898
-				pins = "PC19";
899
-				function = "spi2";
900
-			};
901
-
902
-			spi2_cs0_pins_b: spi2_cs0@1 {
1045
+			/omit-if-no-ref/
1046
+			spi2_cs0_pb_pin: spi2-cs0-pb-pin {
9031047 				pins = "PB14";
9041048 				function = "spi2";
9051049 			};
9061050 
907
-			uart0_pins_a: uart0@0 {
1051
+			/omit-if-no-ref/
1052
+			spi2_pc_pins: spi2-pc-pins {
1053
+				pins = "PC20", "PC21", "PC22";
1054
+				function = "spi2";
1055
+			};
1056
+
1057
+			/omit-if-no-ref/
1058
+			spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1059
+				pins = "PC19";
1060
+				function = "spi2";
1061
+			};
1062
+
1063
+			/omit-if-no-ref/
1064
+			uart0_pb_pins: uart0-pb-pins {
9081065 				pins = "PB22", "PB23";
9091066 				function = "uart0";
9101067 			};
9111068 
912
-			uart2_pins_a: uart2@0 {
913
-				pins = "PI16", "PI17", "PI18", "PI19";
1069
+			/omit-if-no-ref/
1070
+			uart0_pf_pins: uart0-pf-pins {
1071
+				pins = "PF2", "PF4";
1072
+				function = "uart0";
1073
+			};
1074
+
1075
+			/omit-if-no-ref/
1076
+			uart1_pa_pins: uart1-pa-pins {
1077
+				pins = "PA10", "PA11";
1078
+				function = "uart1";
1079
+			};
1080
+
1081
+			/omit-if-no-ref/
1082
+			uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1083
+				pins = "PA12", "PA13";
1084
+				function = "uart1";
1085
+			};
1086
+
1087
+			/omit-if-no-ref/
1088
+			uart2_pa_pins: uart2-pa-pins {
1089
+				pins = "PA2", "PA3";
9141090 				function = "uart2";
9151091 			};
9161092 
917
-			uart3_pins_a: uart3@0 {
918
-				pins = "PG6", "PG7", "PG8", "PG9";
1093
+			/omit-if-no-ref/
1094
+			uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1095
+				pins = "PA0", "PA1";
1096
+				function = "uart2";
1097
+			};
1098
+
1099
+			/omit-if-no-ref/
1100
+			uart2_pi_pins: uart2-pi-pins {
1101
+				pins = "PI18", "PI19";
1102
+				function = "uart2";
1103
+			};
1104
+
1105
+			/omit-if-no-ref/
1106
+			uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1107
+				pins = "PI16", "PI17";
1108
+				function = "uart2";
1109
+			};
1110
+
1111
+			/omit-if-no-ref/
1112
+			uart3_pg_pins: uart3-pg-pins {
1113
+				pins = "PG6", "PG7";
9191114 				function = "uart3";
9201115 			};
9211116 
922
-			uart3_pins_b: uart3@1 {
1117
+			/omit-if-no-ref/
1118
+			uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1119
+				pins = "PG8", "PG9";
1120
+				function = "uart3";
1121
+			};
1122
+
1123
+			/omit-if-no-ref/
1124
+			uart3_ph_pins: uart3-ph-pins {
9231125 				pins = "PH0", "PH1";
9241126 				function = "uart3";
9251127 			};
9261128 
927
-			uart4_pins_a: uart4@0 {
1129
+			/omit-if-no-ref/
1130
+			uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1131
+				pins = "PH2", "PH3";
1132
+				function = "uart3";
1133
+			};
1134
+
1135
+			/omit-if-no-ref/
1136
+			uart4_pg_pins: uart4-pg-pins {
9281137 				pins = "PG10", "PG11";
9291138 				function = "uart4";
9301139 			};
9311140 
932
-			uart4_pins_b: uart4@1 {
1141
+			/omit-if-no-ref/
1142
+			uart4_ph_pins: uart4-ph-pins {
9331143 				pins = "PH4", "PH5";
9341144 				function = "uart4";
9351145 			};
9361146 
937
-			uart5_pins_a: uart5@0 {
1147
+			/omit-if-no-ref/
1148
+			uart5_ph_pins: uart5-ph-pins {
1149
+				pins = "PH6", "PH7";
1150
+				function = "uart5";
1151
+			};
1152
+
1153
+			/omit-if-no-ref/
1154
+			uart5_pi_pins: uart5-pi-pins {
9381155 				pins = "PI10", "PI11";
9391156 				function = "uart5";
9401157 			};
9411158 
942
-			uart6_pins_a: uart6@0 {
1159
+			/omit-if-no-ref/
1160
+			uart6_pa_pins: uart6-pa-pins {
1161
+				pins = "PA12", "PA13";
1162
+				function = "uart6";
1163
+			};
1164
+
1165
+			/omit-if-no-ref/
1166
+			uart6_pi_pins: uart6-pi-pins {
9431167 				pins = "PI12", "PI13";
9441168 				function = "uart6";
9451169 			};
9461170 
947
-			uart7_pins_a: uart7@0 {
1171
+			/omit-if-no-ref/
1172
+			uart7_pa_pins: uart7-pa-pins {
1173
+				pins = "PA14", "PA15";
1174
+				function = "uart7";
1175
+			};
1176
+
1177
+			/omit-if-no-ref/
1178
+			uart7_pi_pins: uart7-pi-pins {
9481179 				pins = "PI20", "PI21";
9491180 				function = "uart7";
9501181 			};
....@@ -965,6 +1196,8 @@
9651196 		wdt: watchdog@1c20c90 {
9661197 			compatible = "allwinner,sun4i-a10-wdt";
9671198 			reg = <0x01c20c90 0x10>;
1199
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1200
+			clocks = <&osc24M>;
9681201 		};
9691202 
9701203 		rtc: rtc@1c20d00 {
....@@ -1185,6 +1418,8 @@
11851418 			reg = <0x01c2ac00 0x400>;
11861419 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
11871420 			clocks = <&ccu CLK_APB1_I2C0>;
1421
+			pinctrl-names = "default";
1422
+			pinctrl-0 = <&i2c0_pins>;
11881423 			status = "disabled";
11891424 			#address-cells = <1>;
11901425 			#size-cells = <0>;
....@@ -1196,6 +1431,8 @@
11961431 			reg = <0x01c2b000 0x400>;
11971432 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
11981433 			clocks = <&ccu CLK_APB1_I2C1>;
1434
+			pinctrl-names = "default";
1435
+			pinctrl-0 = <&i2c1_pins>;
11991436 			status = "disabled";
12001437 			#address-cells = <1>;
12011438 			#size-cells = <0>;
....@@ -1207,6 +1444,8 @@
12071444 			reg = <0x01c2b400 0x400>;
12081445 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
12091446 			clocks = <&ccu CLK_APB1_I2C2>;
1447
+			pinctrl-names = "default";
1448
+			pinctrl-0 = <&i2c2_pins>;
12101449 			status = "disabled";
12111450 			#address-cells = <1>;
12121451 			#size-cells = <0>;
....@@ -1218,6 +1457,8 @@
12181457 			reg = <0x01c2b800 0x400>;
12191458 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
12201459 			clocks = <&ccu CLK_APB1_I2C3>;
1460
+			pinctrl-names = "default";
1461
+			pinctrl-0 = <&i2c3_pins>;
12211462 			status = "disabled";
12221463 			#address-cells = <1>;
12231464 			#size-cells = <0>;
....@@ -1279,8 +1520,12 @@
12791520 			snps,fixed-burst;
12801521 			snps,force_sf_dma_mode;
12811522 			status = "disabled";
1282
-			#address-cells = <1>;
1283
-			#size-cells = <0>;
1523
+
1524
+			gmac_mdio: mdio {
1525
+				compatible = "snps,dwmac-mdio";
1526
+				#address-cells = <1>;
1527
+				#size-cells = <0>;
1528
+			};
12841529 		};
12851530 
12861531 		hstimer@1c60000 {
....@@ -1294,7 +1539,7 @@
12941539 		};
12951540 
12961541 		gic: interrupt-controller@1c81000 {
1297
-			compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1542
+			compatible = "arm,gic-400";
12981543 			reg = <0x01c81000 0x1000>,
12991544 			      <0x01c82000 0x2000>,
13001545 			      <0x01c84000 0x2000>,