add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/sun4i-a10.dtsi
..
..
@@ -184,6 +184,26 @@
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 		status = "disabled";
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 	};
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186
 
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+	pmu {
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+		compatible = "arm,cortex-a8-pmu";
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+		interrupts = <3>;
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+	};
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+
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+	reserved-memory {
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+		#address-cells = <1>;
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+		#size-cells = <1>;
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+		ranges;
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+
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+		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
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+		default-pool {
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+			compatible = "shared-dma-pool";
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+			size = <0x6000000>;
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+			alloc-ranges = <0x40000000 0x10000000>;
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+			reusable;
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+			linux,cma-default;
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+		};
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+	};
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+
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 	soc {
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 		compatible = "simple-bus";
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 		#address-cells = <1>;
..
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@@ -224,6 +244,19 @@
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 					status = "disabled";
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 				};
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 			};
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+
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+			sram_c: sram@1d00000 {
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+				compatible = "mmio-sram";
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+				reg = <0x01d00000 0xd0000>;
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+				#address-cells = <1>;
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+				#size-cells = <1>;
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+				ranges = <0 0x01d00000 0xd0000>;
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+
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+				ve_sram: sram-section@0 {
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+					compatible = "allwinner,sun4i-a10-sram-c1";
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+					reg = <0x000000 0x80000>;
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+				};
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+			};
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 		};
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261
 
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 		dma: dma-controller@1c02000 {
..
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@@ -234,7 +267,7 @@
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 			#dma-cells = <2>;
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 		};
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269
 
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-		nfc: nand@1c03000 {
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+		nfc: nand-controller@1c03000 {
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 			compatible = "allwinner,sun4i-a10-nand";
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 			reg = <0x01c03000 0x1000>;
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 			interrupts = <37>;
..
..
@@ -309,6 +342,7 @@
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 				      "tcon-ch0",
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 				      "tcon-ch1";
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 			clock-output-names = "tcon0-pixel-clock";
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+			#clock-cells = <0>;
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 			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
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347
 
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 			ports {
..
..
@@ -358,6 +392,7 @@
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 				      "tcon-ch0",
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 				      "tcon-ch1";
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 			clock-output-names = "tcon1-pixel-clock";
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+			#clock-cells = <0>;
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 			dmas = <&dma SUN4I_DMA_DEDICATED 15>;
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397
 
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 			ports {
..
..
@@ -392,6 +427,17 @@
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 					};
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 				};
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 			};
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+		};
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+
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+		video-codec@1c0e000 {
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+			compatible = "allwinner,sun4i-a10-video-engine";
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+			reg = <0x01c0e000 0x1000>;
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+			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
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+				 <&ccu CLK_DRAM_VE>;
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+			clock-names = "ahb", "mod", "ram";
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+			resets = <&ccu RST_VE>;
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+			interrupts = <53>;
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+			allwinner,sram = <&ve_sram 1>;
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 		};
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442
 
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 		mmc0: mmc@1c0f000 {
..
..
@@ -450,13 +496,14 @@
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 			phy-names = "usb";
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 			extcon = <&usbphy 0>;
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 			allwinner,sram = <&otg_sram 1>;
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+			dr_mode = "otg";
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 			status = "disabled";
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 		};
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502
 
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 		usbphy: phy@1c13400 {
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 			#phy-cells = <1>;
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 			compatible = "allwinner,sun4i-a10-usb-phy";
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-			reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
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+			reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
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 			reg-names = "phy_ctrl", "pmu1", "pmu2";
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 			clocks = <&ccu CLK_USB_PHY>;
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 			clock-names = "usb_phy";
..
..
@@ -577,6 +624,16 @@
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 			status = "disabled";
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 		};
579
626
 
627
+		csi1: csi@1c1d000 {
628
+			compatible = "allwinner,sun4i-a10-csi1";
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+			reg = <0x01c1d000 0x1000>;
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+			interrupts = <43>;
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+			clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>;
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+			clock-names = "bus", "ram";
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+			resets = <&ccu RST_CSI1>;
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+			status = "disabled";
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+		};
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+
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 		spi3: spi@1c1f000 {
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 			compatible = "allwinner,sun4i-a10-spi";
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 			reg = <0x01c1f000 0x1000>;
..
..
@@ -621,6 +678,31 @@
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 			can0_ph_pins: can0-ph-pins {
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 				pins = "PH20", "PH21";
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 				function = "can";
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+			};
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+
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+			/omit-if-no-ref/
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+			csi1_8bits_pg_pins: csi1-8bits-pg-pins {
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+				pins = "PG0", "PG2", "PG3", "PG4", "PG5",
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+				       "PG6", "PG7", "PG8", "PG9", "PG10",
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+				       "PG11";
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+				function = "csi1";
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+			};
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+
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+			/omit-if-no-ref/
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+			csi1_24bits_ph_pins: csi1-24bits-ph-pins {
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+				pins = "PH0", "PH1", "PH2", "PH3", "PH4",
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+				       "PH5", "PH6", "PH7", "PH8", "PH9",
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+				       "PH10", "PH11", "PH12", "PH13", "PH14",
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+				       "PH15", "PH16", "PH17", "PH18", "PH19",
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+				       "PH20", "PH21", "PH22", "PH23", "PH24",
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+				       "PH25", "PH26", "PH27";
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+				function = "csi1";
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+			};
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+
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+			/omit-if-no-ref/
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+			csi1_clk_pg_pin: csi1-clk-pg-pin {
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+				pins = "PG1";
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+				function = "csi1";
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 			};
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707
 
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 			emac_pins: emac0-pins {
..
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@@ -760,13 +842,20 @@
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 		timer@1c20c00 {
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 			compatible = "allwinner,sun4i-a10-timer";
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 			reg = <0x01c20c00 0x90>;
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-			interrupts = <22>;
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+			interrupts = <22>,
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+				     <23>,
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+				     <24>,
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+				     <25>,
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+				     <67>,
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+				     <68>;
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 			clocks = <&osc24M>;
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 		};
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 		wdt: watchdog@1c20c90 {
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 			compatible = "allwinner,sun4i-a10-wdt";
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 			reg = <0x01c20c90 0x10>;
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+			interrupts = <24>;
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+			clocks = <&osc24M>;
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 		};
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860
 
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 		rtc: rtc@1c20d00 {