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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/socfpga_arria10.dtsi
....@@ -1,17 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0
12 /*
23  * Copyright Altera Corporation (C) 2014. All rights reserved.
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms and conditions of the GNU General Public License,
6
- * version 2, as published by the Free Software Foundation.
7
- *
8
- * This program is distributed in the hope it will be useful, but WITHOUT
9
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11
- * more details.
12
- *
13
- * You should have received a copy of the GNU General Public License along with
14
- * this program.  If not, see <http://www.gnu.org/licenses/>.
154  */
165 
176 #include <dt-bindings/interrupt-controller/arm-gic.h>
....@@ -79,6 +68,8 @@
7968 				#dma-requests = <32>;
8069 				clocks = <&l4_main_clk>;
8170 				clock-names = "apb_pclk";
71
+				resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
72
+				reset-names = "dma", "dma-ocp";
8273 			};
8374 		};
8475 
....@@ -377,10 +368,25 @@
377368 						clk-gate = <0xC8 11>;
378369 					};
379370 
380
-					nand_clk: nand_clk {
371
+					nand_x_clk: nand_x_clk {
381372 						#clock-cells = <0>;
382373 						compatible = "altr,socfpga-a10-gate-clk";
383374 						clocks = <&l4_mp_clk>;
375
+						clk-gate = <0xC8 10>;
376
+					};
377
+
378
+					nand_ecc_clk: nand_ecc_clk {
379
+						#clock-cells = <0>;
380
+						compatible = "altr,socfpga-a10-gate-clk";
381
+						clocks = <&nand_x_clk>;
382
+						clk-gate = <0xC8 10>;
383
+					};
384
+
385
+					nand_clk: nand_clk {
386
+						#clock-cells = <0>;
387
+						compatible = "altr,socfpga-a10-gate-clk";
388
+						clocks = <&nand_x_clk>;
389
+						fixed-divider = <4>;
384390 						clk-gate = <0xC8 10>;
385391 					};
386392 
....@@ -414,7 +420,7 @@
414420 		};
415421 
416422 		gmac0: ethernet@ff800000 {
417
-			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
423
+			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
418424 			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
419425 			reg = <0xff800000 0x2000>;
420426 			interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
....@@ -425,17 +431,17 @@
425431 			snps,perfect-filter-entries = <128>;
426432 			tx-fifo-depth = <4096>;
427433 			rx-fifo-depth = <16384>;
428
-			clocks = <&l4_mp_clk>;
429
-			clock-names = "stmmaceth";
430
-			resets = <&rst EMAC0_RESET>;
431
-			reset-names = "stmmaceth";
434
+			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
435
+			clock-names = "stmmaceth", "ptp_ref";
436
+			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
437
+			reset-names = "stmmaceth", "stmmaceth-ocp";
432438 			snps,axi-config = <&socfpga_axi_setup>;
433439 			status = "disabled";
434440 		};
435441 
436442 		gmac1: ethernet@ff802000 {
437
-			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
438
-			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
443
+			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
444
+			altr,sysmgr-syscon = <&sysmgr 0x48 8>;
439445 		        reg = <0xff802000 0x2000>;
440446 			interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
441447 			interrupt-names = "macirq";
....@@ -445,17 +451,17 @@
445451 			snps,perfect-filter-entries = <128>;
446452 			tx-fifo-depth = <4096>;
447453 			rx-fifo-depth = <16384>;
448
-			clocks = <&l4_mp_clk>;
449
-			clock-names = "stmmaceth";
450
-			resets = <&rst EMAC1_RESET>;
451
-			reset-names = "stmmaceth";
454
+			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
455
+			clock-names = "stmmaceth", "ptp_ref";
456
+			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
457
+			reset-names = "stmmaceth", "stmmaceth-ocp";
452458 			snps,axi-config = <&socfpga_axi_setup>;
453459 			status = "disabled";
454460 		};
455461 
456462 		gmac2: ethernet@ff804000 {
457
-			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
458
-			altr,sysmgr-syscon = <&sysmgr 0x4C 0>;
463
+			compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac";
464
+			altr,sysmgr-syscon = <&sysmgr 0x4C 16>;
459465 			reg = <0xff804000 0x2000>;
460466 			interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
461467 			interrupt-names = "macirq";
....@@ -465,8 +471,10 @@
465471 			snps,perfect-filter-entries = <128>;
466472 			tx-fifo-depth = <4096>;
467473 			rx-fifo-depth = <16384>;
468
-			clocks = <&l4_mp_clk>;
469
-			clock-names = "stmmaceth";
474
+			clocks = <&l4_mp_clk>, <&peri_emac_ptp_clk>;
475
+			clock-names = "stmmaceth", "ptp_ref";
476
+			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
477
+			reset-names = "stmmaceth", "stmmaceth-ocp";
470478 			snps,axi-config = <&socfpga_axi_setup>;
471479 			status = "disabled";
472480 		};
....@@ -476,6 +484,7 @@
476484 			#size-cells = <0>;
477485 			compatible = "snps,dw-apb-gpio";
478486 			reg = <0xffc02900 0x100>;
487
+			resets = <&rst GPIO0_RESET>;
479488 			status = "disabled";
480489 
481490 			porta: gpio-controller@0 {
....@@ -495,6 +504,7 @@
495504 			#size-cells = <0>;
496505 			compatible = "snps,dw-apb-gpio";
497506 			reg = <0xffc02a00 0x100>;
507
+			resets = <&rst GPIO1_RESET>;
498508 			status = "disabled";
499509 
500510 			portb: gpio-controller@0 {
....@@ -514,6 +524,7 @@
514524 			#size-cells = <0>;
515525 			compatible = "snps,dw-apb-gpio";
516526 			reg = <0xffc02b00 0x100>;
527
+			resets = <&rst GPIO2_RESET>;
517528 			status = "disabled";
518529 
519530 			portc: gpio-controller@0 {
....@@ -544,6 +555,7 @@
544555 			reg = <0xffc02200 0x100>;
545556 			interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
546557 			clocks = <&l4_sp_clk>;
558
+			resets = <&rst I2C0_RESET>;
547559 			status = "disabled";
548560 		};
549561 
....@@ -554,6 +566,7 @@
554566 			reg = <0xffc02300 0x100>;
555567 			interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
556568 			clocks = <&l4_sp_clk>;
569
+			resets = <&rst I2C1_RESET>;
557570 			status = "disabled";
558571 		};
559572 
....@@ -564,6 +577,7 @@
564577 			reg = <0xffc02400 0x100>;
565578 			interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
566579 			clocks = <&l4_sp_clk>;
580
+			resets = <&rst I2C2_RESET>;
567581 			status = "disabled";
568582 		};
569583 
....@@ -574,6 +588,7 @@
574588 			reg = <0xffc02500 0x100>;
575589 			interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
576590 			clocks = <&l4_sp_clk>;
591
+			resets = <&rst I2C3_RESET>;
577592 			status = "disabled";
578593 		};
579594 
....@@ -584,6 +599,7 @@
584599 			reg = <0xffc02600 0x100>;
585600 			interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
586601 			clocks = <&l4_sp_clk>;
602
+			resets = <&rst I2C4_RESET>;
587603 			status = "disabled";
588604 		};
589605 
....@@ -596,6 +612,8 @@
596612 			num-cs = <4>;
597613 			/*32bit_access;*/
598614 			clocks = <&spi_m_clk>;
615
+			resets = <&rst SPIM0_RESET>;
616
+			reset-names = "spi";
599617 			status = "disabled";
600618 		};
601619 
....@@ -610,6 +628,8 @@
610628 			tx-dma-channel = <&pdma 16>;
611629 			rx-dma-channel = <&pdma 17>;
612630 			clocks = <&spi_m_clk>;
631
+			resets = <&rst SPIM1_RESET>;
632
+			reset-names = "spi";
613633 			status = "disabled";
614634 		};
615635 
....@@ -638,19 +658,21 @@
638658 			fifo-depth = <0x400>;
639659 			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
640660 			clock-names = "biu", "ciu";
661
+			resets = <&rst SDMMC_RESET>;
641662 			status = "disabled";
642663 		};
643664 
644665 		nand: nand@ffb90000 {
645666 			#address-cells = <1>;
646
-			#size-cells = <1>;
667
+			#size-cells = <0>;
647668 			compatible = "altr,socfpga-denali-nand";
648669 			reg = <0xffb90000 0x72000>,
649670 			      <0xffb80000 0x10000>;
650671 			reg-names = "nand_data", "denali_reg";
651672 			interrupts = <0 99 4>;
652
-			dma-mask = <0xffffffff>;
653
-			clocks = <&nand_clk>;
673
+			clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
674
+			clock-names = "nand", "nand_x", "ecc";
675
+			resets = <&rst NAND_RESET>;
654676 			status = "disabled";
655677 		};
656678 
....@@ -735,6 +757,8 @@
735757 			cdns,fifo-width = <4>;
736758 			cdns,trigger-address = <0x00000000>;
737759 			clocks = <&qspi_clk>;
760
+			resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
761
+			reset-names = "qspi", "qspi-ocp";
738762 			status = "disabled";
739763 		};
740764 
....@@ -760,7 +784,7 @@
760784 		timer@ffffc600 {
761785 			compatible = "arm,cortex-a9-twd-timer";
762786 			reg = <0xffffc600 0x100>;
763
-			interrupts = <1 13 0xf04>;
787
+			interrupts = <1 13 0xf01>;
764788 			clocks = <&mpu_periph_clk>;
765789 		};
766790 
....@@ -770,6 +794,8 @@
770794 			reg = <0xffc02700 0x100>;
771795 			clocks = <&l4_sp_clk>;
772796 			clock-names = "timer";
797
+			resets = <&rst SPTIMER0_RESET>;
798
+			reset-names = "timer";
773799 		};
774800 
775801 		timer1: timer1@ffc02800 {
....@@ -778,6 +804,8 @@
778804 			reg = <0xffc02800 0x100>;
779805 			clocks = <&l4_sp_clk>;
780806 			clock-names = "timer";
807
+			resets = <&rst SPTIMER1_RESET>;
808
+			reset-names = "timer";
781809 		};
782810 
783811 		timer2: timer2@ffd00000 {
....@@ -786,6 +814,8 @@
786814 			reg = <0xffd00000 0x100>;
787815 			clocks = <&l4_sys_free_clk>;
788816 			clock-names = "timer";
817
+			resets = <&rst L4SYSTIMER0_RESET>;
818
+			reset-names = "timer";
789819 		};
790820 
791821 		timer3: timer3@ffd00100 {
....@@ -794,6 +824,8 @@
794824 			reg = <0xffd00100 0x100>;
795825 			clocks = <&l4_sys_free_clk>;
796826 			clock-names = "timer";
827
+			resets = <&rst L4SYSTIMER1_RESET>;
828
+			reset-names = "timer";
797829 		};
798830 
799831 		uart0: serial0@ffc02000 {
....@@ -803,6 +835,7 @@
803835 			reg-shift = <2>;
804836 			reg-io-width = <4>;
805837 			clocks = <&l4_sp_clk>;
838
+			resets = <&rst UART0_RESET>;
806839 			status = "disabled";
807840 		};
808841 
....@@ -813,6 +846,7 @@
813846 			reg-shift = <2>;
814847 			reg-io-width = <4>;
815848 			clocks = <&l4_sp_clk>;
849
+			resets = <&rst UART1_RESET>;
816850 			status = "disabled";
817851 		};
818852 
....@@ -853,6 +887,7 @@
853887 			reg = <0xffd00200 0x100>;
854888 			interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
855889 			clocks = <&l4_sys_free_clk>;
890
+			resets = <&rst L4WD0_RESET>;
856891 			status = "disabled";
857892 		};
858893 
....@@ -861,6 +896,7 @@
861896 			reg = <0xffd00300 0x100>;
862897 			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
863898 			clocks = <&l4_sys_free_clk>;
899
+			resets = <&rst L4WD1_RESET>;
864900 			status = "disabled";
865901 		};
866902 	};