hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/arm/boot/dts/sh73a0.dtsi
....@@ -1,6 +1,6 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * Device Tree Source for the SH73A0 SoC
3
+ * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC
44 *
55 * Copyright (C) 2012 Renesas Solutions Corp.
66 */
....@@ -39,11 +39,18 @@
3939 };
4040 };
4141
42
+ timer@f0000200 {
43
+ compatible = "arm,cortex-a9-global-timer";
44
+ reg = <0xf0000200 0x100>;
45
+ interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
46
+ clocks = <&periph_clk>;
47
+ };
48
+
4249 timer@f0000600 {
4350 compatible = "arm,cortex-a9-twd-timer";
4451 reg = <0xf0000600 0x20>;
4552 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
46
- clocks = <&twd_clk>;
53
+ clocks = <&periph_clk>;
4754 };
4855
4956 gic: interrupt-controller@f0001000 {
....@@ -92,7 +99,7 @@
9299 };
93100
94101 cmt1: timer@e6138000 {
95
- compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
102
+ compatible = "renesas,sh73a0-cmt1";
96103 reg = <0xe6138000 0x200>;
97104 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
98105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
....@@ -110,14 +117,14 @@
110117 <0xe6900020 1>,
111118 <0xe6900040 1>,
112119 <0xe6900060 1>;
113
- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
114
- GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
115
- GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
116
- GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
117
- GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
118
- GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
119
- GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
120
- GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
120
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
121
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
122
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
123
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
124
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
125
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
126
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
127
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
121128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
122129 power-domains = <&pd_a4s>;
123130 control-parent;
....@@ -132,14 +139,14 @@
132139 <0xe6900024 1>,
133140 <0xe6900044 1>,
134141 <0xe6900064 1>;
135
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
136
- GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
137
- GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
138
- GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
139
- GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
140
- GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
141
- GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
142
- GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
142
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
143
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
144
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
145
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
146
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
147
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
148
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
149
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
143150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
144151 power-domains = <&pd_a4s>;
145152 control-parent;
....@@ -154,14 +161,14 @@
154161 <0xe6900028 1>,
155162 <0xe6900048 1>,
156163 <0xe6900068 1>;
157
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
158
- GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
159
- GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
160
- GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
161
- GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
162
- GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
163
- GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
164
- GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
164
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
165
+ <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
166
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
167
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
168
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
169
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
170
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
171
+ <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
165172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
166173 power-domains = <&pd_a4s>;
167174 control-parent;
....@@ -176,14 +183,14 @@
176183 <0xe690002c 1>,
177184 <0xe690004c 1>,
178185 <0xe690006c 1>;
179
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
180
- GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
181
- GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
182
- GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
183
- GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
184
- GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
185
- GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
186
- GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
186
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
187
+ <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
188
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
189
+ <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
190
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
191
+ <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
192
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
193
+ <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
187194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
188195 power-domains = <&pd_a4s>;
189196 control-parent;
....@@ -194,10 +201,10 @@
194201 #size-cells = <0>;
195202 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
196203 reg = <0xe6820000 0x425>;
197
- interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
198
- GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
199
- GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
200
- GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
204
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
205
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
206
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
207
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
201208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
202209 power-domains = <&pd_a3sp>;
203210 status = "disabled";
....@@ -208,10 +215,10 @@
208215 #size-cells = <0>;
209216 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
210217 reg = <0xe6822000 0x425>;
211
- interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
212
- GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
213
- GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
214
- GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
218
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
219
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
220
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
221
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
215222 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
216223 power-domains = <&pd_a3sp>;
217224 status = "disabled";
....@@ -222,10 +229,10 @@
222229 #size-cells = <0>;
223230 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
224231 reg = <0xe6824000 0x425>;
225
- interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
226
- GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
227
- GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
228
- GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
232
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
233
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
234
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
235
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
229236 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
230237 power-domains = <&pd_a3sp>;
231238 status = "disabled";
....@@ -236,10 +243,10 @@
236243 #size-cells = <0>;
237244 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
238245 reg = <0xe6826000 0x425>;
239
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
240
- GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
241
- GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
242
- GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
246
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
247
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
248
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
249
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
243250 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
244251 power-domains = <&pd_a3sp>;
245252 status = "disabled";
....@@ -250,10 +257,10 @@
250257 #size-cells = <0>;
251258 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
252259 reg = <0xe6828000 0x425>;
253
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
254
- GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
255
- GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
256
- GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
260
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
261
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
262
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
263
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
257264 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
258265 power-domains = <&pd_c5>;
259266 status = "disabled";
....@@ -262,8 +269,8 @@
262269 mmcif: mmc@e6bd0000 {
263270 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
264271 reg = <0xe6bd0000 0x100>;
265
- interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
266
- GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
272
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
273
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
267274 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
268275 power-domains = <&pd_a3sp>;
269276 reg-io-width = <4>;
....@@ -314,12 +321,12 @@
314321 status = "disabled";
315322 };
316323
317
- sdhi0: sd@ee100000 {
324
+ sdhi0: mmc@ee100000 {
318325 compatible = "renesas,sdhi-sh73a0";
319326 reg = <0xee100000 0x100>;
320
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
321
- GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
322
- GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
327
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
328
+ <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
329
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
323330 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
324331 power-domains = <&pd_a3sp>;
325332 cap-sd-highspeed;
....@@ -327,11 +334,11 @@
327334 };
328335
329336 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
330
- sdhi1: sd@ee120000 {
337
+ sdhi1: mmc@ee120000 {
331338 compatible = "renesas,sdhi-sh73a0";
332339 reg = <0xee120000 0x100>;
333
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
334
- GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
340
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
341
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
335342 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
336343 power-domains = <&pd_a3sp>;
337344 disable-wp;
....@@ -339,11 +346,11 @@
339346 status = "disabled";
340347 };
341348
342
- sdhi2: sd@ee140000 {
349
+ sdhi2: mmc@ee140000 {
343350 compatible = "renesas,sdhi-sh73a0";
344351 reg = <0xee140000 0x100>;
345
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
346
- GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
352
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
353
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
347354 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
348355 power-domains = <&pd_a3sp>;
349356 disable-wp;
....@@ -441,7 +448,7 @@
441448 status = "disabled";
442449 };
443450
444
- pfc: pin-controller@e6050000 {
451
+ pfc: pinctrl@e6050000 {
445452 compatible = "renesas,pfc-sh73a0";
446453 reg = <0xe6050000 0x8000>,
447454 <0xe605801c 0x1c>;
....@@ -577,6 +584,7 @@
577584 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
578585 reg = <0xec230000 0x400>;
579586 interrupts = <GIC_SPI 146 0x4>;
587
+ clocks = <&mstp3_clks SH73A0_CLK_FSI>;
580588 power-domains = <&pd_a4mp>;
581589 status = "disabled";
582590 };
....@@ -612,19 +620,25 @@
612620 extal2_clk: extal2 {
613621 compatible = "fixed-clock";
614622 #clock-cells = <0>;
623
+ /* This value must be overridden by the board. */
624
+ clock-frequency = <0>;
615625 };
616626 extcki_clk: extcki {
617627 compatible = "fixed-clock";
618628 #clock-cells = <0>;
629
+ /* This value can be overridden by the board. */
630
+ clock-frequency = <0>;
619631 };
620632 fsiack_clk: fsiack {
621633 compatible = "fixed-clock";
622634 #clock-cells = <0>;
635
+ /* This value can be overridden by the board. */
623636 clock-frequency = <0>;
624637 };
625638 fsibck_clk: fsibck {
626639 compatible = "fixed-clock";
627640 #clock-cells = <0>;
641
+ /* This value can be overridden by the board. */
628642 clock-frequency = <0>;
629643 };
630644
....@@ -812,7 +826,7 @@
812826 clock-div = <13>;
813827 clock-mult = <1>;
814828 };
815
- twd_clk: twd {
829
+ periph_clk: periph {
816830 compatible = "fixed-factor-clock";
817831 clocks = <&cpg_clocks SH73A0_CLK_Z>;
818832 #clock-cells = <0>;