.. | .. |
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1 | 1 | // SPDX-License-Identifier: GPL-2.0 |
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2 | 2 | /* |
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3 | | - * Device Tree Source for the SH73A0 SoC |
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| 3 | + * Device Tree Source for the SH-Mobile AG5 (R8A73A00/SH73A0) SoC |
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4 | 4 | * |
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5 | 5 | * Copyright (C) 2012 Renesas Solutions Corp. |
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6 | 6 | */ |
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.. | .. |
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39 | 39 | }; |
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40 | 40 | }; |
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41 | 41 | |
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| 42 | + timer@f0000200 { |
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| 43 | + compatible = "arm,cortex-a9-global-timer"; |
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| 44 | + reg = <0xf0000200 0x100>; |
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| 45 | + interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; |
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| 46 | + clocks = <&periph_clk>; |
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| 47 | + }; |
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| 48 | + |
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42 | 49 | timer@f0000600 { |
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43 | 50 | compatible = "arm,cortex-a9-twd-timer"; |
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44 | 51 | reg = <0xf0000600 0x20>; |
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45 | 52 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; |
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46 | | - clocks = <&twd_clk>; |
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| 53 | + clocks = <&periph_clk>; |
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47 | 54 | }; |
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48 | 55 | |
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49 | 56 | gic: interrupt-controller@f0001000 { |
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.. | .. |
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92 | 99 | }; |
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93 | 100 | |
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94 | 101 | cmt1: timer@e6138000 { |
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95 | | - compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; |
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| 102 | + compatible = "renesas,sh73a0-cmt1"; |
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96 | 103 | reg = <0xe6138000 0x200>; |
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97 | 104 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
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98 | 105 | clocks = <&mstp3_clks SH73A0_CLK_CMT1>; |
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.. | .. |
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110 | 117 | <0xe6900020 1>, |
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111 | 118 | <0xe6900040 1>, |
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112 | 119 | <0xe6900060 1>; |
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113 | | - interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH |
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114 | | - GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH |
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115 | | - GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH |
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116 | | - GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH |
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117 | | - GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH |
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118 | | - GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH |
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119 | | - GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH |
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120 | | - GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
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| 120 | + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
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| 121 | + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
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| 122 | + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
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| 123 | + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
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| 124 | + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
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| 125 | + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
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| 126 | + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
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| 127 | + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
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121 | 128 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
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122 | 129 | power-domains = <&pd_a4s>; |
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123 | 130 | control-parent; |
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.. | .. |
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132 | 139 | <0xe6900024 1>, |
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133 | 140 | <0xe6900044 1>, |
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134 | 141 | <0xe6900064 1>; |
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135 | | - interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH |
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136 | | - GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH |
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137 | | - GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH |
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138 | | - GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH |
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139 | | - GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH |
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140 | | - GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH |
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141 | | - GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH |
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142 | | - GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
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| 142 | + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
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| 143 | + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
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| 144 | + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
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| 145 | + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
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| 146 | + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
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| 147 | + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
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| 148 | + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
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| 149 | + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
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143 | 150 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
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144 | 151 | power-domains = <&pd_a4s>; |
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145 | 152 | control-parent; |
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.. | .. |
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154 | 161 | <0xe6900028 1>, |
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155 | 162 | <0xe6900048 1>, |
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156 | 163 | <0xe6900068 1>; |
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157 | | - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH |
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158 | | - GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH |
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159 | | - GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH |
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160 | | - GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH |
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161 | | - GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH |
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162 | | - GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH |
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163 | | - GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH |
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164 | | - GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
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| 164 | + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
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| 165 | + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
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| 166 | + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
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| 167 | + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
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| 168 | + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
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| 169 | + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
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| 170 | + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, |
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| 171 | + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
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165 | 172 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
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166 | 173 | power-domains = <&pd_a4s>; |
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167 | 174 | control-parent; |
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.. | .. |
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176 | 183 | <0xe690002c 1>, |
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177 | 184 | <0xe690004c 1>, |
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178 | 185 | <0xe690006c 1>; |
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179 | | - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH |
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180 | | - GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH |
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181 | | - GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH |
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182 | | - GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH |
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183 | | - GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH |
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184 | | - GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH |
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185 | | - GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH |
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186 | | - GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
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| 186 | + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, |
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| 187 | + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
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| 188 | + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, |
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| 189 | + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, |
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| 190 | + <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, |
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| 191 | + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, |
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| 192 | + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, |
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| 193 | + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
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187 | 194 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
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188 | 195 | power-domains = <&pd_a4s>; |
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189 | 196 | control-parent; |
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.. | .. |
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194 | 201 | #size-cells = <0>; |
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195 | 202 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
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196 | 203 | reg = <0xe6820000 0x425>; |
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197 | | - interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH |
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198 | | - GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH |
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199 | | - GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH |
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200 | | - GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
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| 204 | + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, |
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| 205 | + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, |
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| 206 | + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, |
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| 207 | + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
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201 | 208 | clocks = <&mstp1_clks SH73A0_CLK_IIC0>; |
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202 | 209 | power-domains = <&pd_a3sp>; |
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203 | 210 | status = "disabled"; |
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.. | .. |
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208 | 215 | #size-cells = <0>; |
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209 | 216 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
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210 | 217 | reg = <0xe6822000 0x425>; |
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211 | | - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH |
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212 | | - GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH |
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213 | | - GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH |
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214 | | - GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
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| 218 | + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
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| 219 | + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
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| 220 | + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
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| 221 | + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
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215 | 222 | clocks = <&mstp3_clks SH73A0_CLK_IIC1>; |
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216 | 223 | power-domains = <&pd_a3sp>; |
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217 | 224 | status = "disabled"; |
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.. | .. |
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222 | 229 | #size-cells = <0>; |
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223 | 230 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
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224 | 231 | reg = <0xe6824000 0x425>; |
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225 | | - interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH |
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226 | | - GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH |
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227 | | - GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH |
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228 | | - GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
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| 232 | + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, |
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| 233 | + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, |
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| 234 | + <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, |
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| 235 | + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
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229 | 236 | clocks = <&mstp0_clks SH73A0_CLK_IIC2>; |
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230 | 237 | power-domains = <&pd_a3sp>; |
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231 | 238 | status = "disabled"; |
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.. | .. |
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236 | 243 | #size-cells = <0>; |
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237 | 244 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
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238 | 245 | reg = <0xe6826000 0x425>; |
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239 | | - interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH |
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240 | | - GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH |
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241 | | - GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH |
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242 | | - GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
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| 246 | + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
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| 247 | + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
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| 248 | + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
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| 249 | + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
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243 | 250 | clocks = <&mstp4_clks SH73A0_CLK_IIC3>; |
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244 | 251 | power-domains = <&pd_a3sp>; |
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245 | 252 | status = "disabled"; |
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.. | .. |
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250 | 257 | #size-cells = <0>; |
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251 | 258 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
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252 | 259 | reg = <0xe6828000 0x425>; |
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253 | | - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH |
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254 | | - GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH |
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255 | | - GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH |
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256 | | - GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
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| 260 | + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
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| 261 | + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
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| 262 | + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
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| 263 | + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
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257 | 264 | clocks = <&mstp4_clks SH73A0_CLK_IIC4>; |
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258 | 265 | power-domains = <&pd_c5>; |
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259 | 266 | status = "disabled"; |
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.. | .. |
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262 | 269 | mmcif: mmc@e6bd0000 { |
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263 | 270 | compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif"; |
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264 | 271 | reg = <0xe6bd0000 0x100>; |
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265 | | - interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH |
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266 | | - GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
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| 272 | + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, |
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| 273 | + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
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267 | 274 | clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; |
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268 | 275 | power-domains = <&pd_a3sp>; |
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269 | 276 | reg-io-width = <4>; |
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.. | .. |
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314 | 321 | status = "disabled"; |
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315 | 322 | }; |
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316 | 323 | |
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317 | | - sdhi0: sd@ee100000 { |
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| 324 | + sdhi0: mmc@ee100000 { |
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318 | 325 | compatible = "renesas,sdhi-sh73a0"; |
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319 | 326 | reg = <0xee100000 0x100>; |
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320 | | - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH |
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321 | | - GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH |
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322 | | - GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
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| 327 | + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, |
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| 328 | + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, |
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| 329 | + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
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323 | 330 | clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; |
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324 | 331 | power-domains = <&pd_a3sp>; |
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325 | 332 | cap-sd-highspeed; |
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.. | .. |
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327 | 334 | }; |
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328 | 335 | |
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329 | 336 | /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ |
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330 | | - sdhi1: sd@ee120000 { |
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| 337 | + sdhi1: mmc@ee120000 { |
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331 | 338 | compatible = "renesas,sdhi-sh73a0"; |
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332 | 339 | reg = <0xee120000 0x100>; |
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333 | | - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH |
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334 | | - GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
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| 340 | + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
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| 341 | + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
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335 | 342 | clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; |
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336 | 343 | power-domains = <&pd_a3sp>; |
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337 | 344 | disable-wp; |
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.. | .. |
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339 | 346 | status = "disabled"; |
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340 | 347 | }; |
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341 | 348 | |
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342 | | - sdhi2: sd@ee140000 { |
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| 349 | + sdhi2: mmc@ee140000 { |
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343 | 350 | compatible = "renesas,sdhi-sh73a0"; |
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344 | 351 | reg = <0xee140000 0x100>; |
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345 | | - interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH |
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346 | | - GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
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| 352 | + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
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| 353 | + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
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347 | 354 | clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; |
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348 | 355 | power-domains = <&pd_a3sp>; |
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349 | 356 | disable-wp; |
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.. | .. |
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441 | 448 | status = "disabled"; |
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442 | 449 | }; |
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443 | 450 | |
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444 | | - pfc: pin-controller@e6050000 { |
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| 451 | + pfc: pinctrl@e6050000 { |
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445 | 452 | compatible = "renesas,pfc-sh73a0"; |
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446 | 453 | reg = <0xe6050000 0x8000>, |
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447 | 454 | <0xe605801c 0x1c>; |
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.. | .. |
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577 | 584 | compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; |
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578 | 585 | reg = <0xec230000 0x400>; |
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579 | 586 | interrupts = <GIC_SPI 146 0x4>; |
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| 587 | + clocks = <&mstp3_clks SH73A0_CLK_FSI>; |
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580 | 588 | power-domains = <&pd_a4mp>; |
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581 | 589 | status = "disabled"; |
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582 | 590 | }; |
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.. | .. |
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612 | 620 | extal2_clk: extal2 { |
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613 | 621 | compatible = "fixed-clock"; |
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614 | 622 | #clock-cells = <0>; |
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| 623 | + /* This value must be overridden by the board. */ |
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| 624 | + clock-frequency = <0>; |
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615 | 625 | }; |
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616 | 626 | extcki_clk: extcki { |
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617 | 627 | compatible = "fixed-clock"; |
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618 | 628 | #clock-cells = <0>; |
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| 629 | + /* This value can be overridden by the board. */ |
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| 630 | + clock-frequency = <0>; |
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619 | 631 | }; |
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620 | 632 | fsiack_clk: fsiack { |
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621 | 633 | compatible = "fixed-clock"; |
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622 | 634 | #clock-cells = <0>; |
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| 635 | + /* This value can be overridden by the board. */ |
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623 | 636 | clock-frequency = <0>; |
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624 | 637 | }; |
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625 | 638 | fsibck_clk: fsibck { |
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626 | 639 | compatible = "fixed-clock"; |
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627 | 640 | #clock-cells = <0>; |
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| 641 | + /* This value can be overridden by the board. */ |
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628 | 642 | clock-frequency = <0>; |
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629 | 643 | }; |
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630 | 644 | |
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.. | .. |
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812 | 826 | clock-div = <13>; |
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813 | 827 | clock-mult = <1>; |
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814 | 828 | }; |
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815 | | - twd_clk: twd { |
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| 829 | + periph_clk: periph { |
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816 | 830 | compatible = "fixed-factor-clock"; |
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817 | 831 | clocks = <&cpg_clocks SH73A0_CLK_Z>; |
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818 | 832 | #clock-cells = <0>; |
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