| .. | .. |
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| 18 | 18 | }; |
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| 19 | 19 | |
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| 20 | 20 | cpus { |
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| 21 | | - cpu { |
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| 22 | | - compatible = "arm,arm926ej-s"; |
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| 23 | | - }; |
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| 24 | | - }; |
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| 21 | + #address-cells = <1>; |
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| 22 | + #size-cells = <0>; |
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| 25 | 23 | |
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| 26 | | - interrupt-controller@4a000000 { |
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| 27 | | - compatible = "samsung,s3c2416-irq"; |
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| 24 | + cpu@0 { |
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| 25 | + device_type = "cpu"; |
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| 26 | + compatible = "arm,arm926ej-s"; |
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| 27 | + reg = <0x0>; |
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| 28 | + }; |
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| 28 | 29 | }; |
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| 29 | 30 | |
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| 30 | 31 | clocks: clock-controller@4c000000 { |
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| 31 | 32 | compatible = "samsung,s3c2416-clock"; |
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| 32 | 33 | reg = <0x4c000000 0x40>; |
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| 33 | 34 | #clock-cells = <1>; |
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| 34 | | - }; |
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| 35 | | - |
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| 36 | | - pinctrl@56000000 { |
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| 37 | | - compatible = "samsung,s3c2416-pinctrl"; |
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| 38 | | - }; |
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| 39 | | - |
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| 40 | | - timer@51000000 { |
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| 41 | | - clocks = <&clocks PCLK_PWM>; |
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| 42 | | - clock-names = "timers"; |
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| 43 | | - }; |
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| 44 | | - |
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| 45 | | - uart_0: serial@50000000 { |
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| 46 | | - compatible = "samsung,s3c2440-uart"; |
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| 47 | | - clock-names = "uart", "clk_uart_baud2", |
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| 48 | | - "clk_uart_baud3"; |
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| 49 | | - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, |
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| 50 | | - <&clocks SCLK_UART>; |
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| 51 | | - }; |
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| 52 | | - |
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| 53 | | - uart_1: serial@50004000 { |
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| 54 | | - compatible = "samsung,s3c2440-uart"; |
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| 55 | | - clock-names = "uart", "clk_uart_baud2", |
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| 56 | | - "clk_uart_baud3"; |
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| 57 | | - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, |
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| 58 | | - <&clocks SCLK_UART>; |
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| 59 | | - }; |
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| 60 | | - |
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| 61 | | - uart_2: serial@50008000 { |
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| 62 | | - compatible = "samsung,s3c2440-uart"; |
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| 63 | | - clock-names = "uart", "clk_uart_baud2", |
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| 64 | | - "clk_uart_baud3"; |
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| 65 | | - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, |
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| 66 | | - <&clocks SCLK_UART>; |
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| 67 | 35 | }; |
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| 68 | 36 | |
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| 69 | 37 | uart_3: serial@5000c000 { |
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| .. | .. |
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| 98 | 66 | <&clocks MUX_HSMMC1>; |
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| 99 | 67 | status = "disabled"; |
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| 100 | 68 | }; |
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| 69 | +}; |
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| 101 | 70 | |
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| 102 | | - watchdog: watchdog@53000000 { |
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| 103 | | - interrupts = <1 9 27 3>; |
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| 104 | | - clocks = <&clocks PCLK_WDT>; |
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| 105 | | - clock-names = "watchdog"; |
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| 106 | | - }; |
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| 71 | +&i2c { |
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| 72 | + compatible = "samsung,s3c2440-i2c"; |
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| 73 | + clocks = <&clocks PCLK_I2C0>; |
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| 74 | + clock-names = "i2c"; |
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| 75 | +}; |
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| 107 | 76 | |
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| 108 | | - rtc: rtc@57000000 { |
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| 109 | | - compatible = "samsung,s3c2416-rtc"; |
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| 110 | | - clocks = <&clocks PCLK_RTC>; |
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| 111 | | - clock-names = "rtc"; |
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| 112 | | - }; |
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| 77 | +&intc { |
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| 78 | + compatible = "samsung,s3c2416-irq"; |
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| 79 | +}; |
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| 113 | 80 | |
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| 114 | | - i2c@54000000 { |
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| 115 | | - compatible = "samsung,s3c2440-i2c"; |
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| 116 | | - clocks = <&clocks PCLK_I2C0>; |
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| 117 | | - clock-names = "i2c"; |
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| 118 | | - }; |
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| 81 | +&pinctrl_0 { |
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| 82 | + compatible = "samsung,s3c2416-pinctrl"; |
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| 83 | +}; |
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| 84 | + |
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| 85 | +&rtc { |
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| 86 | + compatible = "samsung,s3c2416-rtc"; |
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| 87 | + clocks = <&clocks PCLK_RTC>; |
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| 88 | + clock-names = "rtc"; |
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| 89 | +}; |
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| 90 | + |
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| 91 | +&timer { |
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| 92 | + clocks = <&clocks PCLK_PWM>; |
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| 93 | + clock-names = "timers"; |
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| 94 | +}; |
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| 95 | + |
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| 96 | +&uart_0 { |
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| 97 | + compatible = "samsung,s3c2440-uart"; |
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| 98 | + clock-names = "uart", "clk_uart_baud2", |
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| 99 | + "clk_uart_baud3"; |
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| 100 | + clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, |
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| 101 | + <&clocks SCLK_UART>; |
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| 102 | +}; |
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| 103 | + |
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| 104 | +&uart_1 { |
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| 105 | + compatible = "samsung,s3c2440-uart"; |
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| 106 | + clock-names = "uart", "clk_uart_baud2", |
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| 107 | + "clk_uart_baud3"; |
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| 108 | + clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, |
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| 109 | + <&clocks SCLK_UART>; |
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| 110 | +}; |
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| 111 | + |
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| 112 | +&uart_2 { |
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| 113 | + compatible = "samsung,s3c2440-uart"; |
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| 114 | + clock-names = "uart", "clk_uart_baud2", |
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| 115 | + "clk_uart_baud3"; |
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| 116 | + clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, |
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| 117 | + <&clocks SCLK_UART>; |
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| 118 | +}; |
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| 119 | + |
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| 120 | +&watchdog { |
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| 121 | + interrupts = <1 9 27 3>; |
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| 122 | + clocks = <&clocks PCLK_WDT>; |
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| 123 | + clock-names = "watchdog"; |
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| 119 | 124 | }; |
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