forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/rv1126.dtsi
....@@ -24,7 +24,6 @@
2424 	interrupt-parent = <&gic>;
2525 
2626 	aliases {
27
-		ethernet0 = &gmac;
2827 		i2c0 = &i2c0;
2928 		i2c1 = &i2c1;
3029 		i2c2 = &i2c2;
....@@ -126,15 +125,16 @@
126125 		clocks = <&cru PLL_APLL>;
127126 		rockchip,bin-scaling-sel = <
128127 			0	5
129
-			1	18
128
+			1	9
130129 		>;
131130 		rockchip,bin-voltage-sel = <
132131 			1	0
133132 		>;
134133 		rockchip,pvtm-voltage-sel = <
135
-			0        106000   1
136
-			106001   112000   2
137
-			112001   999999   3
134
+			0        100500   1
135
+			100501   104500   2
136
+			104501   109500   3
137
+			109501   999999   4
138138 		>;
139139 		rockchip,pvtm-freq = <408000>;
140140 		rockchip,pvtm-volt = <800000>;
....@@ -172,6 +172,7 @@
172172 			opp-microvolt-L1 = <775000 775000 1000000>;
173173 			opp-microvolt-L2 = <775000 775000 1000000>;
174174 			opp-microvolt-L3 = <750000 750000 1000000>;
175
+			opp-microvolt-L4 = <725000 725000 1000000>;
175176 			clock-latency-ns = <40000>;
176177 		};
177178 		opp-1200000000 {
....@@ -181,22 +182,27 @@
181182 			opp-microvolt-L1 = <850000 850000 1000000>;
182183 			opp-microvolt-L2 = <850000 850000 1000000>;
183184 			opp-microvolt-L3 = <825000 825000 1000000>;
185
+			opp-microvolt-L4 = <800000 800000 1000000>;
184186 			clock-latency-ns = <40000>;
185187 		};
186188 		opp-1296000000 {
187189 			opp-hz = /bits/ 64 <1296000000>;
188190 			opp-microvolt = <875000 875000 1000000>;
191
+			opp-microvolt-L0 = <925000 925000 1000000>;
189192 			opp-microvolt-L1 = <875000 875000 1000000>;
190193 			opp-microvolt-L2 = <875000 875000 1000000>;
191194 			opp-microvolt-L3 = <850000 850000 1000000>;
195
+			opp-microvolt-L4 = <825000 825000 1000000>;
192196 			clock-latency-ns = <40000>;
193197 		};
194198 		opp-1416000000 {
195199 			opp-hz = /bits/ 64 <1416000000>;
196200 			opp-microvolt = <925000 925000 1000000>;
201
+			opp-microvolt-L0 = <975000 975000 1000000>;
197202 			opp-microvolt-L1 = <925000 925000 1000000>;
198203 			opp-microvolt-L2 = <925000 925000 1000000>;
199204 			opp-microvolt-L3 = <900000 900000 1000000>;
205
+			opp-microvolt-L4 = <875000 875000 1000000>;
200206 			clock-latency-ns = <40000>;
201207 		};
202208 		opp-1512000000 {
....@@ -205,6 +211,7 @@
205211 			opp-microvolt-L1 = <975000 975000 1000000>;
206212 			opp-microvolt-L2 = <950000 950000 1000000>;
207213 			opp-microvolt-L3 = <925000 925000 1000000>;
214
+			opp-microvolt-L4 = <900000 900000 1000000>;
208215 			clock-latency-ns = <40000>;
209216 		};
210217 	};
....@@ -390,8 +397,6 @@
390397 			console-size = <0x40000>;
391398 			ftrace-size = <0x00000>;
392399 			pmsg-size = <0x40000>;
393
-			mcu-log-size = <0x40000>;
394
-			mcu-log-count = <0x1>;
395400 			status = "disabled";
396401 		};
397402 	};
....@@ -1163,13 +1168,14 @@
11631168 	};
11641169 
11651170 	mipi_dphy: mipi-dphy@ff4d0000 {
1166
-		compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk1808-mipi-dphy";
1167
-		reg = <0xff4d0000 0x500>;
1171
+		compatible = "rockchip,rv1126-mipi-dphy", "rockchip,rk3568-video-phy";
1172
+		reg = <0xff4d0000 0x500>, <0xffb30000 0x500>;
1173
+		reg-names = "phy", "host";
11681174 		assigned-clocks = <&pmucru CLK_MIPIDSIPHY_REF>;
11691175 		assigned-clock-rates = <24000000>;
1170
-		clocks = <&pmucru CLK_MIPIDSIPHY_REF>, <&cru PCLK_DSIPHY>;
1171
-		clock-names = "ref", "pclk";
1172
-		clock-output-names = "mipi_dphy_pll";
1176
+		clocks = <&pmucru CLK_MIPIDSIPHY_REF>,
1177
+			 <&cru PCLK_DSIPHY>, <&cru PCLK_DSIHOST>;
1178
+		clock-names = "ref", "pclk", "pclk_host";
11731179 		#clock-cells = <0>;
11741180 		resets = <&cru SRST_DSIPHY_P>;
11751181 		reset-names = "apb";
....@@ -1625,7 +1631,7 @@
16251631 	};
16261632 
16271633 	pdm: pdm@ff830000 {
1628
-		compatible = "rockchip,rv1126-pdm";
1634
+		compatible = "rockchip,rv1126-pdm", "rockchip,pdm";
16291635 		reg = <0xff830000 0x1000>;
16301636 		clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
16311637 		clock-names = "pdm_clk", "pdm_hclk";
....@@ -1904,12 +1910,12 @@
19041910 		compatible = "rockchip,rv1126-mipi-dsi";
19051911 		reg = <0xffb30000 0x500>;
19061912 		interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1907
-		clocks = <&cru PCLK_DSIHOST>, <&mipi_dphy>;
1908
-		clock-names = "pclk", "hs_clk";
1913
+		clocks = <&cru PCLK_DSIHOST>, <&cru HCLK_PDVO>;
1914
+		clock-names = "pclk", "hclk";
19091915 		resets = <&cru SRST_DSIHOST_P>;
19101916 		reset-names = "apb";
19111917 		phys = <&mipi_dphy>;
1912
-		phy-names = "mipi_dphy";
1918
+		phy-names = "dphy";
19131919 		rockchip,grf = <&grf>;
19141920 		#address-cells = <1>;
19151921 		#size-cells = <0>;
....@@ -2107,7 +2113,7 @@
21072113 	};
21082114 
21092115 	rkvdec: rkvdec@ffb80000 {
2110
-		compatible = "rockchip,rkv-decoder-rv1126", "rockchip,rkv-decoder-v1";
2116
+		compatible = "rockchip,rkv-decoder-v1";
21112117 		reg = <0xffb80000 0x400>;
21122118 		interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
21132119 		interrupt-names = "irq_dec";
....@@ -2125,7 +2131,7 @@
21252131 		iommus = <&rkvdec_mmu>;
21262132 		rockchip,srv = <&mpp_srv>;
21272133 		rockchip,taskqueue-node = <0>;
2128
-		rockchip,resetgroup-node = <1>;
2134
+		rockchip,resetgroup-node = <0>;
21292135 		status = "disabled";
21302136 	};
21312137 
....@@ -2231,7 +2237,7 @@
22312237 		clocks = <&pmucru PLL_GPLL>;
22322238 		rockchip,bin-scaling-sel = <
22332239 			0	37
2234
-			1	43
2240
+			1	40
22352241 		>;
22362242 		rockchip,bin-voltage-sel = <
22372243 			1	0
....@@ -2253,6 +2259,7 @@
22532259 		opp-500000000 {
22542260 			opp-hz = /bits/ 64 <500000000>;
22552261 			opp-microvolt = <750000 750000 1000000>;
2262
+			opp-microvolt-L0 = <800000 800000 1000000>;
22562263 		};
22572264 		opp-594000000 {
22582265 			opp-hz = /bits/ 64 <594000000>;
....@@ -2398,7 +2405,7 @@
23982405 		status = "disabled";
23992406 	};
24002407 
2401
-	sfc: sfc@ffc90000  {
2408
+	sfc: spi@ffc90000  {
24022409 		compatible = "rockchip,sfc";
24032410 		reg = <0xffc90000 0x4000>;
24042411 		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
....@@ -2409,6 +2416,8 @@
24092416 		assigned-clocks = <&cru SCLK_SFC>;
24102417 		assigned-clock-rates = <80000000>;
24112418 		power-domains = <&power RV1126_PD_NVM>;
2419
+		#address-cells = <1>;
2420
+		#size-cells = <0>;
24122421 		status = "disabled";
24132422 	};
24142423 
....@@ -2449,9 +2458,9 @@
24492458 			2	0
24502459 		>;
24512460 		rockchip,pvtm-voltage-sel = <
2452
-			0        112500   1
2453
-			112501   117500   2
2454
-			117501   999999   3
2461
+			0        108500   1
2462
+			108501   113500   2
2463
+			113501   999999   3
24552464 		>;
24562465 		rockchip,pvtm-freq = <396000>;
24572466 		rockchip,pvtm-volt = <800000>;
....@@ -2466,27 +2475,27 @@
24662475 		opp-200000000 {
24672476 			opp-hz = /bits/ 64 <200000000>;
24682477 			opp-microvolt = <750000 750000 1000000>;
2469
-			opp-microvolt-L0 = <800000 800000 1000000>;
2478
+			opp-microvolt-L0 = <775000 775000 1000000>;
24702479 		};
24712480 		opp-300000000 {
24722481 			opp-hz = /bits/ 64 <300000000>;
24732482 			opp-microvolt = <750000 750000 1000000>;
2474
-			opp-microvolt-L0 = <800000 800000 1000000>;
2483
+			opp-microvolt-L0 = <775000 775000 1000000>;
24752484 		};
24762485 		opp-396000000 {
24772486 			opp-hz = /bits/ 64 <396000000>;
24782487 			opp-microvolt = <750000 750000 1000000>;
2479
-			opp-microvolt-L0 = <800000 800000 1000000>;
2488
+			opp-microvolt-L0 = <775000 775000 1000000>;
24802489 		};
24812490 		opp-500000000 {
24822491 			opp-hz = /bits/ 64 <500000000>;
24832492 			opp-microvolt = <750000 750000 1000000>;
2484
-			opp-microvolt-L0 = <800000 800000 1000000>;
2493
+			opp-microvolt-L0 = <775000 775000 1000000>;
24852494 		};
24862495 		opp-600000000 {
24872496 			opp-hz = /bits/ 64 <600000000>;
24882497 			opp-microvolt = <750000 750000 1000000>;
2489
-			opp-microvolt-L0 = <800000 800000 1000000>;
2498
+			opp-microvolt-L0 = <775000 775000 1000000>;
24902499 		};
24912500 		opp-700000000 {
24922501 			opp-hz = /bits/ 64 <700000000>;