forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/rv1108.dtsi
....@@ -32,6 +32,7 @@
3232 			device_type = "cpu";
3333 			compatible = "arm,cortex-a7";
3434 			reg = <0xf00>;
35
+			clock-latency = <40000>;
3536 			clocks = <&cru ARMCLK>;
3637 			#cooling-cells = <2>; /* min followed by max */
3738 			dynamic-power-coefficient = <75>;
....@@ -73,6 +74,7 @@
7374 		compatible = "arm,armv7-timer";
7475 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
7576 			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77
+		arm,cpu-registers-not-fw-configured;
7678 		clock-frequency = <24000000>;
7779 	};
7880 
....@@ -83,7 +85,7 @@
8385 		#clock-cells = <0>;
8486 	};
8587 
86
-	amba {
88
+	amba: bus {
8789 		compatible = "simple-bus";
8890 		#address-cells = <1>;
8991 		#size-cells = <1>;
....@@ -101,7 +103,7 @@
101103 		};
102104 	};
103105 
104
-	bus_intmem@10080000 {
106
+	bus_intmem: sram@10080000 {
105107 		compatible = "mmio-sram";
106108 		reg = <0x10080000 0x2000>;
107109 		#address-cells = <1>;
....@@ -118,6 +120,7 @@
118120 		clock-frequency = <24000000>;
119121 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
120122 		clock-names = "baudclk", "apb_pclk";
123
+		dmas = <&pdma 6>, <&pdma 7>;
121124 		pinctrl-names = "default";
122125 		pinctrl-0 = <&uart2m0_xfer>;
123126 		status = "disabled";
....@@ -132,6 +135,7 @@
132135 		clock-frequency = <24000000>;
133136 		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
134137 		clock-names = "baudclk", "apb_pclk";
138
+		dmas = <&pdma 4>, <&pdma 5>;
135139 		pinctrl-names = "default";
136140 		pinctrl-0 = <&uart1_xfer>;
137141 		status = "disabled";
....@@ -146,6 +150,7 @@
146150 		clock-frequency = <24000000>;
147151 		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
148152 		clock-names = "baudclk", "apb_pclk";
153
+		dmas = <&pdma 2>, <&pdma 3>;
149154 		pinctrl-names = "default";
150155 		pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
151156 		status = "disabled";
....@@ -161,6 +166,7 @@
161166 		clock-names = "i2c", "pclk";
162167 		pinctrl-names = "default";
163168 		pinctrl-0 = <&i2c1_xfer>;
169
+		rockchip,grf = <&grf>;
164170 		status = "disabled";
165171 	};
166172 
....@@ -188,6 +194,7 @@
188194 		clock-names = "i2c", "pclk";
189195 		pinctrl-names = "default";
190196 		pinctrl-0 = <&i2c3_xfer>;
197
+		rockchip,grf = <&grf>;
191198 		status = "disabled";
192199 	};
193200 
....@@ -198,7 +205,7 @@
198205 		clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
199206 		clock-names = "spiclk", "apb_pclk";
200207 		dmas = <&pdma 8>, <&pdma 9>;
201
-		#dma-cells = <2>;
208
+		dma-names = "tx", "rx";
202209 		#address-cells = <1>;
203210 		#size-cells = <0>;
204211 		status = "disabled";
....@@ -210,7 +217,7 @@
210217 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
211218 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
212219 		clock-names = "pwm", "pclk";
213
-		pinctrl-names = "default";
220
+		pinctrl-names = "active";
214221 		pinctrl-0 = <&pwm4_pin>;
215222 		#pwm-cells = <3>;
216223 		status = "disabled";
....@@ -222,7 +229,7 @@
222229 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
223230 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
224231 		clock-names = "pwm", "pclk";
225
-		pinctrl-names = "default";
232
+		pinctrl-names = "active";
226233 		pinctrl-0 = <&pwm5_pin>;
227234 		#pwm-cells = <3>;
228235 		status = "disabled";
....@@ -234,7 +241,7 @@
234241 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
235242 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
236243 		clock-names = "pwm", "pclk";
237
-		pinctrl-names = "default";
244
+		pinctrl-names = "active";
238245 		pinctrl-0 = <&pwm6_pin>;
239246 		#pwm-cells = <3>;
240247 		status = "disabled";
....@@ -246,7 +253,7 @@
246253 		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
247254 		clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
248255 		clock-names = "pwm", "pclk";
249
-		pinctrl-names = "default";
256
+		pinctrl-names = "active";
250257 		pinctrl-0 = <&pwm7_pin>;
251258 		#pwm-cells = <3>;
252259 		status = "disabled";
....@@ -282,6 +289,14 @@
282289 				status = "disabled";
283290 			};
284291 		};
292
+	};
293
+
294
+	timer: timer@10350000 {
295
+		compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
296
+		reg = <0x10350000 0x20>;
297
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
298
+		clocks = <&xin24m>, <&cru PCLK_TIMER>;
299
+		clock-names = "timer", "pclk";
285300 	};
286301 
287302 	watchdog: wdt@10360000 {
....@@ -337,9 +352,9 @@
337352 		clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
338353 		clock-names = "tsadc", "apb_pclk";
339354 		pinctrl-names = "init", "default", "sleep";
340
-		pinctrl-0 = <&otp_gpio>;
355
+		pinctrl-0 = <&otp_pin>;
341356 		pinctrl-1 = <&otp_out>;
342
-		pinctrl-2 = <&otp_gpio>;
357
+		pinctrl-2 = <&otp_pin>;
343358 		resets = <&cru SRST_TSADC>;
344359 		reset-names = "tsadc-apb";
345360 		rockchip,hw-tshut-temp = <120000>;
....@@ -352,7 +367,6 @@
352367 		reg = <0x1038c000 0x100>;
353368 		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
354369 		#io-channel-cells = <1>;
355
-		clock-frequency = <1000000>;
356370 		clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
357371 		clock-names = "saradc", "apb_pclk";
358372 		status = "disabled";
....@@ -368,6 +382,7 @@
368382 		clock-names = "i2c", "pclk";
369383 		pinctrl-names = "default";
370384 		pinctrl-0 = <&i2c0_xfer>;
385
+		rockchip,grf = <&grf>;
371386 		status = "disabled";
372387 	};
373388 
....@@ -437,17 +452,7 @@
437452 		#reset-cells = <1>;
438453 	};
439454 
440
-	nandc: nandc@30100000 {
441
-		compatible = "rockchip,rk-nandc";
442
-		reg = <0x30100000 0x1000>;
443
-		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
444
-		nandc_id = <0>;
445
-		clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
446
-		clock-names = "clk_nandc", "hclk_nandc";
447
-		status = "disabled";
448
-	};
449
-
450
-	emmc: dwmmc@30110000 {
455
+	emmc: mmc@30110000 {
451456 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
452457 		reg = <0x30110000 0x4000>;
453458 		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
....@@ -459,7 +464,7 @@
459464 		status = "disabled";
460465 	};
461466 
462
-	sdio: dwmmc@30120000 {
467
+	sdio: mmc@30120000 {
463468 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
464469 		reg = <0x30120000 0x4000>;
465470 		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
....@@ -471,7 +476,7 @@
471476 		status = "disabled";
472477 	};
473478 
474
-	sdmmc: dwmmc@30130000 {
479
+	sdmmc: mmc@30130000 {
475480 		compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
476481 		reg = <0x30130000 0x4000>;
477482 		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
....@@ -490,7 +495,6 @@
490495 		reg = <0x30140000 0x20000>;
491496 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
492497 		clocks = <&cru HCLK_HOST0>, <&u2phy>;
493
-		clock-names = "usbhost", "utmi";
494498 		phys = <&u2phy_host>;
495499 		phy-names = "usb";
496500 		status = "disabled";
....@@ -501,7 +505,6 @@
501505 		reg = <0x30160000 0x20000>;
502506 		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503507 		clocks = <&cru HCLK_HOST0>, <&u2phy>;
504
-		clock-names = "usbhost", "utmi";
505508 		phys = <&u2phy_host>;
506509 		phy-names = "usb";
507510 		status = "disabled";
....@@ -518,9 +521,30 @@
518521 		g-np-tx-fifo-size = <16>;
519522 		g-rx-fifo-size = <280>;
520523 		g-tx-fifo-size = <256 128 128 64 32 16>;
521
-		g-use-dma;
522524 		phys = <&u2phy_otg>;
523525 		phy-names = "usb2-phy";
526
+		status = "disabled";
527
+	};
528
+
529
+	gmac: eth@30200000 {
530
+		compatible = "rockchip,rv1108-gmac";
531
+		reg = <0x30200000 0x10000>;
532
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
533
+			     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
534
+		interrupt-names = "macirq", "eth_wake_irq";
535
+		clocks = <&cru SCLK_MAC>,
536
+			<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
537
+			<&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
538
+			<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
539
+		clock-names = "stmmaceth",
540
+			"mac_clk_rx", "mac_clk_tx",
541
+			"clk_mac_ref", "clk_mac_refout",
542
+			"aclk_mac", "pclk_mac";
543
+		/* rv1108 only supports an rmii interface */
544
+		phy-mode = "rmii";
545
+		pinctrl-names = "default";
546
+		pinctrl-0 = <&rmii_pins>;
547
+		rockchip,grf = <&grf>;
524548 		status = "disabled";
525549 	};
526550 
....@@ -535,10 +559,6 @@
535559 		      <0x32014000 0x2000>,
536560 		      <0x32016000 0x2000>;
537561 		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
538
-	};
539
-
540
-	rockchip_system_monitor: rockchip-system-monitor {
541
-		compatible = "rockchip,system-monitor";
542562 	};
543563 
544564 	pinctrl: pinctrl {
....@@ -653,6 +673,42 @@
653673 			input-enable;
654674 		};
655675 
676
+		emmc {
677
+			emmc_bus8: emmc-bus8 {
678
+				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
679
+						<2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
680
+						<2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
681
+						<2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
682
+						<2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
683
+						<2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
684
+						<2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
685
+						<2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
686
+			};
687
+
688
+			emmc_clk: emmc-clk {
689
+				rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
690
+			};
691
+
692
+			emmc_cmd: emmc-cmd {
693
+				rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
694
+			};
695
+		};
696
+
697
+		gmac {
698
+			rmii_pins: rmii-pins {
699
+				rockchip,pins =	<1 RK_PC5 2 &pcfg_pull_none>,
700
+						<1 RK_PC3 2 &pcfg_pull_none>,
701
+						<1 RK_PC4 2 &pcfg_pull_none>,
702
+						<1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
703
+						<1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
704
+						<1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
705
+						<1 RK_PB5 3 &pcfg_pull_none>,
706
+						<1 RK_PB6 3 &pcfg_pull_none>,
707
+						<1 RK_PB7 3 &pcfg_pull_none>,
708
+						<1 RK_PC2 3 &pcfg_pull_none>;
709
+			};
710
+		};
711
+
656712 		i2c0 {
657713 			i2c0_xfer: i2c0-xfer {
658714 				rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
....@@ -673,7 +729,7 @@
673729 						<0 RK_PC6 3 &pcfg_pull_none>;
674730 			};
675731 
676
-			i2c2m1_gpio: i2c2m1-gpio {
732
+			i2c2m1_pins: i2c2m1-pins {
677733 				rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
678734 						<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
679735 			};
....@@ -685,7 +741,7 @@
685741 						<1 RK_PD4 2 &pcfg_pull_none>;
686742 			};
687743 
688
-			i2c2m05v_gpio: i2c2m05v-gpio {
744
+			i2c2m05v_pins: i2c2m05v-pins {
689745 				rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
690746 						<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
691747 			};
....@@ -771,12 +827,48 @@
771827 			};
772828 		};
773829 
830
+		spim0 {
831
+			spim0_clk: spim0-clk {
832
+				rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
833
+			};
834
+
835
+			spim0_cs0: spim0-cs0 {
836
+				rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
837
+			};
838
+
839
+			spim0_tx: spim0-tx {
840
+				rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
841
+			};
842
+
843
+			spim0_rx: spim0-rx {
844
+				rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
845
+			};
846
+		};
847
+
848
+		spim1 {
849
+			spim1_clk: spim1-clk {
850
+				rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
851
+			};
852
+
853
+			spim1_cs0: spim1-cs0 {
854
+				rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
855
+			};
856
+
857
+			spim1_rx: spim1-rx {
858
+				rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
859
+			};
860
+
861
+			spim1_tx: spim1-tx {
862
+				rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
863
+			};
864
+		};
865
+
774866 		tsadc {
775867 			otp_out: otp-out {
776868 				rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
777869 			};
778870 
779
-			otp_gpio: otp-gpio {
871
+			otp_pin: otp-pin {
780872 				rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
781873 			};
782874 		};
....@@ -784,7 +876,7 @@
784876 		uart0 {
785877 			uart0_xfer: uart0-xfer {
786878 				rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
787
-						<3 RK_PA5 1 &pcfg_pull_up>;
879
+						<3 RK_PA5 1 &pcfg_pull_none>;
788880 			};
789881 
790882 			uart0_cts: uart0-cts {
....@@ -795,7 +887,7 @@
795887 				rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
796888 			};
797889 
798
-			uart0_rts_gpio: uart0-rts-gpio {
890
+			uart0_rts_pin: uart0-rts-pin {
799891 				rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
800892 			};
801893 		};
....@@ -803,7 +895,7 @@
803895 		uart1 {
804896 			uart1_xfer: uart1-xfer {
805897 				rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
806
-						<1 RK_PD2 1 &pcfg_pull_up>;
898
+						<1 RK_PD2 1 &pcfg_pull_none>;
807899 			};
808900 
809901 			uart1_cts: uart1-cts {
....@@ -818,14 +910,14 @@
818910 		uart2m0 {
819911 			uart2m0_xfer: uart2m0-xfer {
820912 				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
821
-						<2 RK_PD1 1 &pcfg_pull_up>;
913
+						<2 RK_PD1 1 &pcfg_pull_none>;
822914 			};
823915 		};
824916 
825917 		uart2m1 {
826918 			uart2m1_xfer: uart2m1-xfer {
827919 				rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
828
-						<3 RK_PC2 2 &pcfg_pull_up>;
920
+						<3 RK_PC2 2 &pcfg_pull_none>;
829921 			};
830922 		};
831923