.. | .. |
---|
32 | 32 | device_type = "cpu"; |
---|
33 | 33 | compatible = "arm,cortex-a7"; |
---|
34 | 34 | reg = <0xf00>; |
---|
| 35 | + clock-latency = <40000>; |
---|
35 | 36 | clocks = <&cru ARMCLK>; |
---|
36 | 37 | #cooling-cells = <2>; /* min followed by max */ |
---|
37 | 38 | dynamic-power-coefficient = <75>; |
---|
.. | .. |
---|
73 | 74 | compatible = "arm,armv7-timer"; |
---|
74 | 75 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, |
---|
75 | 76 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; |
---|
| 77 | + arm,cpu-registers-not-fw-configured; |
---|
76 | 78 | clock-frequency = <24000000>; |
---|
77 | 79 | }; |
---|
78 | 80 | |
---|
.. | .. |
---|
83 | 85 | #clock-cells = <0>; |
---|
84 | 86 | }; |
---|
85 | 87 | |
---|
86 | | - amba { |
---|
| 88 | + amba: bus { |
---|
87 | 89 | compatible = "simple-bus"; |
---|
88 | 90 | #address-cells = <1>; |
---|
89 | 91 | #size-cells = <1>; |
---|
.. | .. |
---|
101 | 103 | }; |
---|
102 | 104 | }; |
---|
103 | 105 | |
---|
104 | | - bus_intmem@10080000 { |
---|
| 106 | + bus_intmem: sram@10080000 { |
---|
105 | 107 | compatible = "mmio-sram"; |
---|
106 | 108 | reg = <0x10080000 0x2000>; |
---|
107 | 109 | #address-cells = <1>; |
---|
.. | .. |
---|
118 | 120 | clock-frequency = <24000000>; |
---|
119 | 121 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; |
---|
120 | 122 | clock-names = "baudclk", "apb_pclk"; |
---|
| 123 | + dmas = <&pdma 6>, <&pdma 7>; |
---|
121 | 124 | pinctrl-names = "default"; |
---|
122 | 125 | pinctrl-0 = <&uart2m0_xfer>; |
---|
123 | 126 | status = "disabled"; |
---|
.. | .. |
---|
132 | 135 | clock-frequency = <24000000>; |
---|
133 | 136 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; |
---|
134 | 137 | clock-names = "baudclk", "apb_pclk"; |
---|
| 138 | + dmas = <&pdma 4>, <&pdma 5>; |
---|
135 | 139 | pinctrl-names = "default"; |
---|
136 | 140 | pinctrl-0 = <&uart1_xfer>; |
---|
137 | 141 | status = "disabled"; |
---|
.. | .. |
---|
146 | 150 | clock-frequency = <24000000>; |
---|
147 | 151 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; |
---|
148 | 152 | clock-names = "baudclk", "apb_pclk"; |
---|
| 153 | + dmas = <&pdma 2>, <&pdma 3>; |
---|
149 | 154 | pinctrl-names = "default"; |
---|
150 | 155 | pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; |
---|
151 | 156 | status = "disabled"; |
---|
.. | .. |
---|
161 | 166 | clock-names = "i2c", "pclk"; |
---|
162 | 167 | pinctrl-names = "default"; |
---|
163 | 168 | pinctrl-0 = <&i2c1_xfer>; |
---|
| 169 | + rockchip,grf = <&grf>; |
---|
164 | 170 | status = "disabled"; |
---|
165 | 171 | }; |
---|
166 | 172 | |
---|
.. | .. |
---|
188 | 194 | clock-names = "i2c", "pclk"; |
---|
189 | 195 | pinctrl-names = "default"; |
---|
190 | 196 | pinctrl-0 = <&i2c3_xfer>; |
---|
| 197 | + rockchip,grf = <&grf>; |
---|
191 | 198 | status = "disabled"; |
---|
192 | 199 | }; |
---|
193 | 200 | |
---|
.. | .. |
---|
198 | 205 | clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>; |
---|
199 | 206 | clock-names = "spiclk", "apb_pclk"; |
---|
200 | 207 | dmas = <&pdma 8>, <&pdma 9>; |
---|
201 | | - #dma-cells = <2>; |
---|
| 208 | + dma-names = "tx", "rx"; |
---|
202 | 209 | #address-cells = <1>; |
---|
203 | 210 | #size-cells = <0>; |
---|
204 | 211 | status = "disabled"; |
---|
.. | .. |
---|
210 | 217 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
---|
211 | 218 | clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; |
---|
212 | 219 | clock-names = "pwm", "pclk"; |
---|
213 | | - pinctrl-names = "default"; |
---|
| 220 | + pinctrl-names = "active"; |
---|
214 | 221 | pinctrl-0 = <&pwm4_pin>; |
---|
215 | 222 | #pwm-cells = <3>; |
---|
216 | 223 | status = "disabled"; |
---|
.. | .. |
---|
222 | 229 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
---|
223 | 230 | clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; |
---|
224 | 231 | clock-names = "pwm", "pclk"; |
---|
225 | | - pinctrl-names = "default"; |
---|
| 232 | + pinctrl-names = "active"; |
---|
226 | 233 | pinctrl-0 = <&pwm5_pin>; |
---|
227 | 234 | #pwm-cells = <3>; |
---|
228 | 235 | status = "disabled"; |
---|
.. | .. |
---|
234 | 241 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
---|
235 | 242 | clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; |
---|
236 | 243 | clock-names = "pwm", "pclk"; |
---|
237 | | - pinctrl-names = "default"; |
---|
| 244 | + pinctrl-names = "active"; |
---|
238 | 245 | pinctrl-0 = <&pwm6_pin>; |
---|
239 | 246 | #pwm-cells = <3>; |
---|
240 | 247 | status = "disabled"; |
---|
.. | .. |
---|
246 | 253 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
---|
247 | 254 | clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>; |
---|
248 | 255 | clock-names = "pwm", "pclk"; |
---|
249 | | - pinctrl-names = "default"; |
---|
| 256 | + pinctrl-names = "active"; |
---|
250 | 257 | pinctrl-0 = <&pwm7_pin>; |
---|
251 | 258 | #pwm-cells = <3>; |
---|
252 | 259 | status = "disabled"; |
---|
.. | .. |
---|
282 | 289 | status = "disabled"; |
---|
283 | 290 | }; |
---|
284 | 291 | }; |
---|
| 292 | + }; |
---|
| 293 | + |
---|
| 294 | + timer: timer@10350000 { |
---|
| 295 | + compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer"; |
---|
| 296 | + reg = <0x10350000 0x20>; |
---|
| 297 | + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 298 | + clocks = <&xin24m>, <&cru PCLK_TIMER>; |
---|
| 299 | + clock-names = "timer", "pclk"; |
---|
285 | 300 | }; |
---|
286 | 301 | |
---|
287 | 302 | watchdog: wdt@10360000 { |
---|
.. | .. |
---|
337 | 352 | clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; |
---|
338 | 353 | clock-names = "tsadc", "apb_pclk"; |
---|
339 | 354 | pinctrl-names = "init", "default", "sleep"; |
---|
340 | | - pinctrl-0 = <&otp_gpio>; |
---|
| 355 | + pinctrl-0 = <&otp_pin>; |
---|
341 | 356 | pinctrl-1 = <&otp_out>; |
---|
342 | | - pinctrl-2 = <&otp_gpio>; |
---|
| 357 | + pinctrl-2 = <&otp_pin>; |
---|
343 | 358 | resets = <&cru SRST_TSADC>; |
---|
344 | 359 | reset-names = "tsadc-apb"; |
---|
345 | 360 | rockchip,hw-tshut-temp = <120000>; |
---|
.. | .. |
---|
352 | 367 | reg = <0x1038c000 0x100>; |
---|
353 | 368 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
---|
354 | 369 | #io-channel-cells = <1>; |
---|
355 | | - clock-frequency = <1000000>; |
---|
356 | 370 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; |
---|
357 | 371 | clock-names = "saradc", "apb_pclk"; |
---|
358 | 372 | status = "disabled"; |
---|
.. | .. |
---|
368 | 382 | clock-names = "i2c", "pclk"; |
---|
369 | 383 | pinctrl-names = "default"; |
---|
370 | 384 | pinctrl-0 = <&i2c0_xfer>; |
---|
| 385 | + rockchip,grf = <&grf>; |
---|
371 | 386 | status = "disabled"; |
---|
372 | 387 | }; |
---|
373 | 388 | |
---|
.. | .. |
---|
437 | 452 | #reset-cells = <1>; |
---|
438 | 453 | }; |
---|
439 | 454 | |
---|
440 | | - nandc: nandc@30100000 { |
---|
441 | | - compatible = "rockchip,rk-nandc"; |
---|
442 | | - reg = <0x30100000 0x1000>; |
---|
443 | | - interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
---|
444 | | - nandc_id = <0>; |
---|
445 | | - clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>; |
---|
446 | | - clock-names = "clk_nandc", "hclk_nandc"; |
---|
447 | | - status = "disabled"; |
---|
448 | | - }; |
---|
449 | | - |
---|
450 | | - emmc: dwmmc@30110000 { |
---|
| 455 | + emmc: mmc@30110000 { |
---|
451 | 456 | compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; |
---|
452 | 457 | reg = <0x30110000 0x4000>; |
---|
453 | 458 | interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
---|
.. | .. |
---|
459 | 464 | status = "disabled"; |
---|
460 | 465 | }; |
---|
461 | 466 | |
---|
462 | | - sdio: dwmmc@30120000 { |
---|
| 467 | + sdio: mmc@30120000 { |
---|
463 | 468 | compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; |
---|
464 | 469 | reg = <0x30120000 0x4000>; |
---|
465 | 470 | interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
---|
.. | .. |
---|
471 | 476 | status = "disabled"; |
---|
472 | 477 | }; |
---|
473 | 478 | |
---|
474 | | - sdmmc: dwmmc@30130000 { |
---|
| 479 | + sdmmc: mmc@30130000 { |
---|
475 | 480 | compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc"; |
---|
476 | 481 | reg = <0x30130000 0x4000>; |
---|
477 | 482 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
---|
.. | .. |
---|
490 | 495 | reg = <0x30140000 0x20000>; |
---|
491 | 496 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
---|
492 | 497 | clocks = <&cru HCLK_HOST0>, <&u2phy>; |
---|
493 | | - clock-names = "usbhost", "utmi"; |
---|
494 | 498 | phys = <&u2phy_host>; |
---|
495 | 499 | phy-names = "usb"; |
---|
496 | 500 | status = "disabled"; |
---|
.. | .. |
---|
501 | 505 | reg = <0x30160000 0x20000>; |
---|
502 | 506 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
---|
503 | 507 | clocks = <&cru HCLK_HOST0>, <&u2phy>; |
---|
504 | | - clock-names = "usbhost", "utmi"; |
---|
505 | 508 | phys = <&u2phy_host>; |
---|
506 | 509 | phy-names = "usb"; |
---|
507 | 510 | status = "disabled"; |
---|
.. | .. |
---|
518 | 521 | g-np-tx-fifo-size = <16>; |
---|
519 | 522 | g-rx-fifo-size = <280>; |
---|
520 | 523 | g-tx-fifo-size = <256 128 128 64 32 16>; |
---|
521 | | - g-use-dma; |
---|
522 | 524 | phys = <&u2phy_otg>; |
---|
523 | 525 | phy-names = "usb2-phy"; |
---|
| 526 | + status = "disabled"; |
---|
| 527 | + }; |
---|
| 528 | + |
---|
| 529 | + gmac: eth@30200000 { |
---|
| 530 | + compatible = "rockchip,rv1108-gmac"; |
---|
| 531 | + reg = <0x30200000 0x10000>; |
---|
| 532 | + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
---|
| 533 | + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 534 | + interrupt-names = "macirq", "eth_wake_irq"; |
---|
| 535 | + clocks = <&cru SCLK_MAC>, |
---|
| 536 | + <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>, |
---|
| 537 | + <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, |
---|
| 538 | + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; |
---|
| 539 | + clock-names = "stmmaceth", |
---|
| 540 | + "mac_clk_rx", "mac_clk_tx", |
---|
| 541 | + "clk_mac_ref", "clk_mac_refout", |
---|
| 542 | + "aclk_mac", "pclk_mac"; |
---|
| 543 | + /* rv1108 only supports an rmii interface */ |
---|
| 544 | + phy-mode = "rmii"; |
---|
| 545 | + pinctrl-names = "default"; |
---|
| 546 | + pinctrl-0 = <&rmii_pins>; |
---|
| 547 | + rockchip,grf = <&grf>; |
---|
524 | 548 | status = "disabled"; |
---|
525 | 549 | }; |
---|
526 | 550 | |
---|
.. | .. |
---|
535 | 559 | <0x32014000 0x2000>, |
---|
536 | 560 | <0x32016000 0x2000>; |
---|
537 | 561 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; |
---|
538 | | - }; |
---|
539 | | - |
---|
540 | | - rockchip_system_monitor: rockchip-system-monitor { |
---|
541 | | - compatible = "rockchip,system-monitor"; |
---|
542 | 562 | }; |
---|
543 | 563 | |
---|
544 | 564 | pinctrl: pinctrl { |
---|
.. | .. |
---|
653 | 673 | input-enable; |
---|
654 | 674 | }; |
---|
655 | 675 | |
---|
| 676 | + emmc { |
---|
| 677 | + emmc_bus8: emmc-bus8 { |
---|
| 678 | + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>, |
---|
| 679 | + <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>, |
---|
| 680 | + <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>, |
---|
| 681 | + <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>, |
---|
| 682 | + <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>, |
---|
| 683 | + <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>, |
---|
| 684 | + <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>, |
---|
| 685 | + <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>; |
---|
| 686 | + }; |
---|
| 687 | + |
---|
| 688 | + emmc_clk: emmc-clk { |
---|
| 689 | + rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>; |
---|
| 690 | + }; |
---|
| 691 | + |
---|
| 692 | + emmc_cmd: emmc-cmd { |
---|
| 693 | + rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>; |
---|
| 694 | + }; |
---|
| 695 | + }; |
---|
| 696 | + |
---|
| 697 | + gmac { |
---|
| 698 | + rmii_pins: rmii-pins { |
---|
| 699 | + rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>, |
---|
| 700 | + <1 RK_PC3 2 &pcfg_pull_none>, |
---|
| 701 | + <1 RK_PC4 2 &pcfg_pull_none>, |
---|
| 702 | + <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>, |
---|
| 703 | + <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>, |
---|
| 704 | + <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>, |
---|
| 705 | + <1 RK_PB5 3 &pcfg_pull_none>, |
---|
| 706 | + <1 RK_PB6 3 &pcfg_pull_none>, |
---|
| 707 | + <1 RK_PB7 3 &pcfg_pull_none>, |
---|
| 708 | + <1 RK_PC2 3 &pcfg_pull_none>; |
---|
| 709 | + }; |
---|
| 710 | + }; |
---|
| 711 | + |
---|
656 | 712 | i2c0 { |
---|
657 | 713 | i2c0_xfer: i2c0-xfer { |
---|
658 | 714 | rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>, |
---|
.. | .. |
---|
673 | 729 | <0 RK_PC6 3 &pcfg_pull_none>; |
---|
674 | 730 | }; |
---|
675 | 731 | |
---|
676 | | - i2c2m1_gpio: i2c2m1-gpio { |
---|
| 732 | + i2c2m1_pins: i2c2m1-pins { |
---|
677 | 733 | rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, |
---|
678 | 734 | <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; |
---|
679 | 735 | }; |
---|
.. | .. |
---|
685 | 741 | <1 RK_PD4 2 &pcfg_pull_none>; |
---|
686 | 742 | }; |
---|
687 | 743 | |
---|
688 | | - i2c2m05v_gpio: i2c2m05v-gpio { |
---|
| 744 | + i2c2m05v_pins: i2c2m05v-pins { |
---|
689 | 745 | rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>, |
---|
690 | 746 | <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; |
---|
691 | 747 | }; |
---|
.. | .. |
---|
771 | 827 | }; |
---|
772 | 828 | }; |
---|
773 | 829 | |
---|
| 830 | + spim0 { |
---|
| 831 | + spim0_clk: spim0-clk { |
---|
| 832 | + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>; |
---|
| 833 | + }; |
---|
| 834 | + |
---|
| 835 | + spim0_cs0: spim0-cs0 { |
---|
| 836 | + rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>; |
---|
| 837 | + }; |
---|
| 838 | + |
---|
| 839 | + spim0_tx: spim0-tx { |
---|
| 840 | + rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; |
---|
| 841 | + }; |
---|
| 842 | + |
---|
| 843 | + spim0_rx: spim0-rx { |
---|
| 844 | + rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; |
---|
| 845 | + }; |
---|
| 846 | + }; |
---|
| 847 | + |
---|
| 848 | + spim1 { |
---|
| 849 | + spim1_clk: spim1-clk { |
---|
| 850 | + rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>; |
---|
| 851 | + }; |
---|
| 852 | + |
---|
| 853 | + spim1_cs0: spim1-cs0 { |
---|
| 854 | + rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>; |
---|
| 855 | + }; |
---|
| 856 | + |
---|
| 857 | + spim1_rx: spim1-rx { |
---|
| 858 | + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>; |
---|
| 859 | + }; |
---|
| 860 | + |
---|
| 861 | + spim1_tx: spim1-tx { |
---|
| 862 | + rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>; |
---|
| 863 | + }; |
---|
| 864 | + }; |
---|
| 865 | + |
---|
774 | 866 | tsadc { |
---|
775 | 867 | otp_out: otp-out { |
---|
776 | 868 | rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; |
---|
777 | 869 | }; |
---|
778 | 870 | |
---|
779 | | - otp_gpio: otp-gpio { |
---|
| 871 | + otp_pin: otp-pin { |
---|
780 | 872 | rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; |
---|
781 | 873 | }; |
---|
782 | 874 | }; |
---|
.. | .. |
---|
784 | 876 | uart0 { |
---|
785 | 877 | uart0_xfer: uart0-xfer { |
---|
786 | 878 | rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>, |
---|
787 | | - <3 RK_PA5 1 &pcfg_pull_up>; |
---|
| 879 | + <3 RK_PA5 1 &pcfg_pull_none>; |
---|
788 | 880 | }; |
---|
789 | 881 | |
---|
790 | 882 | uart0_cts: uart0-cts { |
---|
.. | .. |
---|
795 | 887 | rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>; |
---|
796 | 888 | }; |
---|
797 | 889 | |
---|
798 | | - uart0_rts_gpio: uart0-rts-gpio { |
---|
| 890 | + uart0_rts_pin: uart0-rts-pin { |
---|
799 | 891 | rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; |
---|
800 | 892 | }; |
---|
801 | 893 | }; |
---|
.. | .. |
---|
803 | 895 | uart1 { |
---|
804 | 896 | uart1_xfer: uart1-xfer { |
---|
805 | 897 | rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>, |
---|
806 | | - <1 RK_PD2 1 &pcfg_pull_up>; |
---|
| 898 | + <1 RK_PD2 1 &pcfg_pull_none>; |
---|
807 | 899 | }; |
---|
808 | 900 | |
---|
809 | 901 | uart1_cts: uart1-cts { |
---|
.. | .. |
---|
818 | 910 | uart2m0 { |
---|
819 | 911 | uart2m0_xfer: uart2m0-xfer { |
---|
820 | 912 | rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>, |
---|
821 | | - <2 RK_PD1 1 &pcfg_pull_up>; |
---|
| 913 | + <2 RK_PD1 1 &pcfg_pull_none>; |
---|
822 | 914 | }; |
---|
823 | 915 | }; |
---|
824 | 916 | |
---|
825 | 917 | uart2m1 { |
---|
826 | 918 | uart2m1_xfer: uart2m1-xfer { |
---|
827 | 919 | rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>, |
---|
828 | | - <3 RK_PC2 2 &pcfg_pull_up>; |
---|
| 920 | + <3 RK_PC2 2 &pcfg_pull_none>; |
---|
829 | 921 | }; |
---|
830 | 922 | }; |
---|
831 | 923 | |
---|