add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/rk3288-veyron.dtsi
..
..
@@ -10,6 +10,10 @@
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 #include "rk3288.dtsi"
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11
 
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 / {
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+	chosen {
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+		stdout-path = "serial2:115200n8";
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+	};
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+
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 	/*
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 	 * The default coreboot on veyron devices ignores memory@0 nodes
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 	 * and would instead create another memory node.
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@@ -19,13 +23,12 @@
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 		reg = <0x0 0x0 0x0 0x80000000>;
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 	};
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-	gpio_keys: gpio-keys {
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-		compatible = "gpio-keys";
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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26
 
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+	power_button: power-button {
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+		compatible = "gpio-keys";
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 		pinctrl-names = "default";
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 		pinctrl-0 = <&pwr_key_l>;
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+
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 		power {
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 			label = "Power";
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 			gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_LOW>;
..
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@@ -55,11 +58,13 @@
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 		clocks = <&rk808 RK808_CLKOUT1>;
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 		clock-names = "ext_clock";
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 		pinctrl-names = "default";
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-		pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
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+		pinctrl-0 = <&wifi_enable_h>;
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62
 
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 		/*
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-		 * On the module itself this is one of these (depending
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-		 * on the actual card populated):
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+		 * Depending on the actual card populated GPIO4 D4
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+		 * correspond to one of these signals on the module:
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+		 *
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+		 * D4:
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 		 * - SDIO_RESET_L_WL_REG_ON
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 		 * - PDN (power down when low)
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 		 */
..
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@@ -91,10 +96,31 @@
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 		regulator-boot-on;
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 		vin-supply = <&vcc_5v>;
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 	};
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+
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+	vdd_logic: vdd-logic {
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+		compatible = "pwm-regulator";
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+		regulator-name = "vdd_logic";
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+
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+		pwms = <&pwm1 0 1994 0>;
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+		pwm-supply = <&vcc33_sys>;
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+
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+		pwm-dutycycle-range = <0x7b 0>;
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+		pwm-dutycycle-unit = <0x94>;
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+
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+		regulator-always-on;
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+		regulator-boot-on;
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+		regulator-min-microvolt = <950000>;
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+		regulator-max-microvolt = <1350000>;
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+		regulator-ramp-delay = <4000>;
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+	};
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 };
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117
 
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 &cpu0 {
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 	cpu0-supply = <&vdd_cpu>;
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+};
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+
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+&cpu_crit {
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+	temperature = <100000>;
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 };
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 /* rk3288-c used in Veyron Chrome-devices has slightly changed OPPs */
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@@ -136,8 +162,18 @@
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 	status = "okay";
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 };
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164
 
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+&gpu_alert0 {
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+	temperature = <72500>;
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+};
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+
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+&gpu_crit {
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+	temperature = <100000>;
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+};
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+
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 &hdmi {
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-	ddc-i2c-bus = <&i2c5>;
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+	pinctrl-names = "default", "unwedge";
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+	pinctrl-0 = <&hdmi_ddc>;
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+	pinctrl-1 = <&hdmi_ddc_unwedge>;
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 	status = "okay";
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 };
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..
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@@ -191,8 +227,7 @@
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 				regulator-max-microvolt = <1250000>;
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 				regulator-ramp-delay = <6001>;
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 				regulator-state-mem {
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-					regulator-on-in-suspend;
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-					regulator-suspend-microvolt = <1000000>;
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+					regulator-off-in-suspend;
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 				};
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 			};
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..
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@@ -309,14 +344,6 @@
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 	i2c-scl-rising-time-ns = <300>;		/* 225ns measured */
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 };
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346
 
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-&i2c5 {
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-	status = "okay";
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-
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-	clock-frequency = <100000>;
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-	i2c-scl-falling-time-ns = <300>;
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-	i2c-scl-rising-time-ns = <1000>;
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-};
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-
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 &io_domains {
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 	status = "okay";
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349
 
..
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@@ -369,14 +396,11 @@
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396
 
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 	rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */
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 	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
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+	rockchip,hw-tshut-temp = <125000>;
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400
 };
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401
 
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402
 &uart0 {
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 	status = "okay";
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-
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-	/* We need to go faster than 24MHz, so adjust clock parents / rates */
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-	assigned-clocks = <&cru SCLK_UART0>;
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-	assigned-clock-rates = <48000000>;
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404
 
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 	/* Pins don't include flow control by default; add that in */
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406
 	pinctrl-names = "default";
..
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@@ -403,6 +427,7 @@
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 &usb_host1 {
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 	status = "okay";
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+	snps,need-phy-for-wake;
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 };
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432
 
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 &usb_otg {
..
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@@ -411,6 +436,7 @@
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 	assigned-clocks = <&cru SCLK_USBPHY480M_SRC>;
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 	assigned-clock-parents = <&usbphy0>;
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 	dr_mode = "host";
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+	snps,need-phy-for-wake;
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 };
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 &vopb {
..
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@@ -426,16 +452,6 @@
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 };
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453
 
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 &pinctrl {
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-	pinctrl-names = "default", "sleep";
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-	pinctrl-0 = <
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-		/* Common for sleep and wake, but no owners */
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-		&global_pwroff
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-	>;
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-	pinctrl-1 = <
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-		/* Common for sleep and wake, but no owners */
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-		&global_pwroff
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-	>;
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-
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455
 	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
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 		bias-disable;
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 		drive-strength = <8>;
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@@ -517,6 +533,14 @@
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 			rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
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 		};
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+		bt_host_wake: bt-host-wake {
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+			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_down>;
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+		};
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+
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+		bt_host_wake_l: bt-host-wake-l {
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+			rockchip,pins = <4 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
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+		};
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+
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 		/*
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 		 * We run sdio0 at max speed; bump up drive strength.
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 		 * We also have external pulls, so disable the internal ones.
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@@ -535,6 +559,24 @@
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 		sdio0_clk: sdio0-clk {
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 			rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;
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 		};
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+
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+		/*
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+		 * These pins are only present on very new veyron boards; on
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+		 * older boards bt_dev_wake is simply always high.  Note that
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+		 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt
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+		 * to map this pin everywhere
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+		 */
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+		bt_dev_wake_sleep: bt-dev-wake-sleep {
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+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;
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+		};
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+
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+		bt_dev_wake_awake: bt-dev-wake-awake {
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+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
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+		};
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+
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+		bt_dev_wake: bt-dev-wake {
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+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
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+		};
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 	};
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581
 
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 	tpm {