forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/rk3288-veyron-speedy.dts
....@@ -7,6 +7,7 @@
77 
88 /dts-v1/;
99 #include "rk3288-veyron-chromebook.dtsi"
10
+#include "rk3288-veyron-broadcom-bluetooth.dtsi"
1011 #include "cros-ec-sbs.dtsi"
1112 
1213 / {
....@@ -16,44 +17,6 @@
1617 		     "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
1718 		     "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
1819 		     "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
19
-
20
-	panel_regulator: panel-regulator {
21
-		compatible = "regulator-fixed";
22
-		enable-active-high;
23
-		gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
24
-		pinctrl-names = "default";
25
-		pinctrl-0 = <&lcd_enable_h>;
26
-		regulator-name = "panel_regulator";
27
-		startup-delay-us = <100000>;
28
-		vin-supply = <&vcc33_sys>;
29
-	};
30
-
31
-	vcc18_lcd: vcc18-lcd {
32
-		compatible = "regulator-fixed";
33
-		enable-active-high;
34
-		gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
35
-		pinctrl-names = "default";
36
-		pinctrl-0 = <&avdd_1v8_disp_en>;
37
-		regulator-name = "vcc18_lcd";
38
-		regulator-always-on;
39
-		regulator-boot-on;
40
-		vin-supply = <&vcc18_wl>;
41
-	};
42
-
43
-	backlight_regulator: backlight-regulator {
44
-		compatible = "regulator-fixed";
45
-		enable-active-high;
46
-		gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
47
-		pinctrl-names = "default";
48
-		pinctrl-0 = <&bl_pwr_en>;
49
-		regulator-name = "backlight_regulator";
50
-		vin-supply = <&vcc33_sys>;
51
-		startup-delay-us = <15000>;
52
-	};
53
-};
54
-
55
-&backlight {
56
-	power-supply = <&backlight_regulator>;
5720 };
5821 
5922 &cpu_alert0 {
....@@ -64,6 +27,10 @@
6427 	temperature = <70000>;
6528 };
6629 
30
+&cpu_crit {
31
+	temperature = <90000>;
32
+};
33
+
6734 &edp {
6835 	/delete-property/pinctrl-names;
6936 	/delete-property/pinctrl-0;
....@@ -71,8 +38,12 @@
7138 	force-hpd;
7239 };
7340 
74
-&panel {
75
-	power-supply= <&panel_regulator>;
41
+&gpu_alert0 {
42
+	temperature = <80000>;
43
+};
44
+
45
+&gpu_crit {
46
+	temperature = <90000>;
7647 };
7748 
7849 &rk808 {
....@@ -83,7 +54,7 @@
8354 &sdmmc {
8455 	disable-wp;
8556 	pinctrl-names = "default";
86
-	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
57
+	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
8758 			&sdmmc_bus4>;
8859 };
8960 
....@@ -101,12 +72,233 @@
10172 	pinctrl-0 = <&vcc50_hdmi_en>;
10273 };
10374 
75
+&gpio0 {
76
+	gpio-line-names = "PMIC_SLEEP_AP",
77
+			  "DDRIO_PWROFF",
78
+			  "DDRIO_RETEN",
79
+			  "TS3A227E_INT_L",
80
+			  "PMIC_INT_L",
81
+			  "PWR_KEY_L",
82
+			  "AP_LID_INT_L",
83
+			  "EC_IN_RW",
84
+
85
+			  "AC_PRESENT_AP",
86
+			  /*
87
+			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
88
+			   * it REC_MODE_L.
89
+			   */
90
+			  "RECOVERY_SW_L",
91
+			  "OTP_OUT",
92
+			  "HOST1_PWR_EN",
93
+			  "USBOTG_PWREN_H",
94
+			  "AP_WARM_RESET_H",
95
+			  "nFALUT2",
96
+			  "I2C0_SDA_PMIC",
97
+
98
+			  "I2C0_SCL_PMIC",
99
+			  "SUSPEND_L",
100
+			  "USB_INT";
101
+};
102
+
103
+&gpio2 {
104
+	gpio-line-names = "CONFIG0",
105
+			  "CONFIG1",
106
+			  "CONFIG2",
107
+			  "",
108
+			  "",
109
+			  "",
110
+			  "",
111
+			  "CONFIG3",
112
+
113
+			  "PWRLIMIT#_CPU",
114
+			  "EMMC_RST_L",
115
+			  "",
116
+			  "",
117
+			  "BL_PWR_EN",
118
+			  "AVDD_1V8_DISP_EN";
119
+};
120
+
121
+&gpio3 {
122
+	gpio-line-names = "FLASH0_D0",
123
+			  "FLASH0_D1",
124
+			  "FLASH0_D2",
125
+			  "FLASH0_D3",
126
+			  "FLASH0_D4",
127
+			  "FLASH0_D5",
128
+			  "FLASH0_D6",
129
+			  "FLASH0_D7",
130
+
131
+			  "",
132
+			  "",
133
+			  "",
134
+			  "",
135
+			  "",
136
+			  "",
137
+			  "",
138
+			  "",
139
+
140
+			  "FLASH0_CS2/EMMC_CMD",
141
+			  "",
142
+			  "FLASH0_DQS/EMMC_CLKO";
143
+};
144
+
145
+&gpio4 {
146
+	gpio-line-names = "",
147
+			  "",
148
+			  "",
149
+			  "",
150
+			  "",
151
+			  "",
152
+			  "",
153
+			  "",
154
+
155
+			  "",
156
+			  "",
157
+			  "",
158
+			  "",
159
+			  "",
160
+			  "",
161
+			  "",
162
+			  "",
163
+
164
+			  "UART0_RXD",
165
+			  "UART0_TXD",
166
+			  "UART0_CTS",
167
+			  "UART0_RTS",
168
+			  "SDIO0_D0",
169
+			  "SDIO0_D1",
170
+			  "SDIO0_D2",
171
+			  "SDIO0_D3",
172
+
173
+			  "SDIO0_CMD",
174
+			  "SDIO0_CLK",
175
+			  "BT_DEV_WAKE",
176
+			  "",
177
+			  "WIFI_ENABLE_H",
178
+			  "BT_ENABLE_L",
179
+			  "WIFI_HOST_WAKE",
180
+			  "BT_HOST_WAKE";
181
+};
182
+
183
+&gpio5 {
184
+	gpio-line-names = "",
185
+			  "",
186
+			  "",
187
+			  "",
188
+			  "",
189
+			  "",
190
+			  "",
191
+			  "",
192
+
193
+			  "",
194
+			  "",
195
+			  "",
196
+			  "",
197
+			  "SPI0_CLK",
198
+			  "SPI0_CS0",
199
+			  "SPI0_TXD",
200
+			  "SPI0_RXD",
201
+
202
+			  "",
203
+			  "",
204
+			  "",
205
+			  "VCC50_HDMI_EN";
206
+};
207
+
208
+&gpio6 {
209
+	gpio-line-names = "I2S0_SCLK",
210
+			  "I2S0_LRCK_RX",
211
+			  "I2S0_LRCK_TX",
212
+			  "I2S0_SDI",
213
+			  "I2S0_SDO0",
214
+			  "HP_DET_H",
215
+			  "ALS_INT",		/* not connected */
216
+			  "INT_CODEC",
217
+
218
+			  "I2S0_CLK",
219
+			  "I2C2_SDA",
220
+			  "I2C2_SCL",
221
+			  "MICDET",
222
+			  "",
223
+			  "",
224
+			  "",
225
+			  "",
226
+
227
+			  "SDMMC_D0",
228
+			  "SDMMC_D1",
229
+			  "SDMMC_D2",
230
+			  "SDMMC_D3",
231
+			  "SDMMC_CLK",
232
+			  "SDMMC_CMD";
233
+};
234
+
235
+&gpio7 {
236
+	gpio-line-names = "LCDC_BL",
237
+			  "PWM_LOG",
238
+			  "BL_EN",
239
+			  "TRACKPAD_INT",
240
+			  "TPM_INT_H",
241
+			  "SDMMC_DET_L",
242
+			  /*
243
+			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
244
+			   * it FW_WP_AP.
245
+			   */
246
+			  "AP_FLASH_WP_L",
247
+			  "EC_INT",
248
+
249
+			  "CPU_NMI",
250
+			  "DVS_OK",
251
+			  "",
252
+			  "EDP_HOTPLUG",
253
+			  "DVS1",
254
+			  "nFALUT1",
255
+			  "LCD_EN",
256
+			  "DVS2",
257
+
258
+			  "VCC5V_GOOD_H",
259
+			  "I2C4_SDA_TP",
260
+			  "I2C4_SCL_TP",
261
+			  "I2C5_SDA_HDMI",
262
+			  "I2C5_SCL_HDMI",
263
+			  "5V_DRV",
264
+			  "UART2_RXD",
265
+			  "UART2_TXD";
266
+};
267
+
268
+&gpio8 {
269
+	gpio-line-names = "RAM_ID0",
270
+			  "RAM_ID1",
271
+			  "RAM_ID2",
272
+			  "RAM_ID3",
273
+			  "I2C1_SDA_TPM",
274
+			  "I2C1_SCL_TPM",
275
+			  "SPI2_CLK",
276
+			  "SPI2_CS0",
277
+
278
+			  "SPI2_RXD",
279
+			  "SPI2_TXD";
280
+};
281
+
104282 &pinctrl {
105
-	backlight {
106
-		bl_pwr_en: bl_pwr_en {
107
-			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
108
-		};
109
-	};
283
+	pinctrl-names = "default", "sleep";
284
+	pinctrl-0 = <
285
+		/* Common for sleep and wake, but no owners */
286
+		&ddr0_retention
287
+		&ddrio_pwroff
288
+		&global_pwroff
289
+
290
+		/* Wake only */
291
+		&suspend_l_wake
292
+	>;
293
+	pinctrl-1 = <
294
+		/* Common for sleep and wake, but no owners */
295
+		&ddr0_retention
296
+		&ddrio_pwroff
297
+		&global_pwroff
298
+
299
+		/* Sleep only */
300
+		&suspend_l_sleep
301
+	>;
110302 
111303 	buck-5v {
112304 		drv_5v: drv-5v {
....@@ -117,16 +309,6 @@
117309 	hdmi {
118310 		vcc50_hdmi_en: vcc50-hdmi-en {
119311 			rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
120
-		};
121
-	};
122
-
123
-	lcd {
124
-		lcd_enable_h: lcd-en {
125
-			rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
126
-		};
127
-
128
-		avdd_1v8_disp_en: avdd-1v8-disp-en {
129
-			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
130312 		};
131313 	};
132314