add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/rk3188.dtsi
..
..
@@ -7,10 +7,18 @@
7
7
 #include <dt-bindings/gpio/gpio.h>
8
8
 #include <dt-bindings/pinctrl/rockchip.h>
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 #include <dt-bindings/clock/rk3188-cru.h>
10
+#include <dt-bindings/power/rk3188-power.h>
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 #include "rk3xxx.dtsi"
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12
 
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 / {
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 	compatible = "rockchip,rk3188";
15
+
16
+	aliases {
17
+		gpio0 = &gpio0;
18
+		gpio1 = &gpio1;
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+		gpio2 = &gpio2;
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+		gpio3 = &gpio3;
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+	};
14
22
 
15
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 	cpus {
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 		#address-cells = <1>;
..
..
@@ -22,38 +30,80 @@
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 			compatible = "arm,cortex-a9";
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 			next-level-cache = <&L2>;
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32
 			reg = <0x0>;
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-			operating-points = <
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-				/* kHz    uV */
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-				1608000 1350000
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-				1416000 1250000
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-				1200000 1150000
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-				1008000 1075000
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-				 816000  975000
32
-				 600000  950000
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-				 504000  925000
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-				 312000  875000
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-			>;
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 			clock-latency = <40000>;
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 			clocks = <&cru ARMCLK>;
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+			operating-points-v2 = <&cpu0_opp_table>;
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+			resets = <&cru SRST_CORE0>;
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 		};
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-		cpu@1 {
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+		cpu1: cpu@1 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			next-level-cache = <&L2>;
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 			reg = <0x1>;
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+			operating-points-v2 = <&cpu0_opp_table>;
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+			resets = <&cru SRST_CORE1>;
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 		};
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-		cpu@2 {
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+		cpu2: cpu@2 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			next-level-cache = <&L2>;
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 			reg = <0x2>;
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+			operating-points-v2 = <&cpu0_opp_table>;
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+			resets = <&cru SRST_CORE2>;
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 		};
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-		cpu@3 {
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+		cpu3: cpu@3 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			next-level-cache = <&L2>;
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 			reg = <0x3>;
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+			operating-points-v2 = <&cpu0_opp_table>;
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+			resets = <&cru SRST_CORE3>;
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 		};
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+	};
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+
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+	cpu0_opp_table: opp_table0 {
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+		compatible = "operating-points-v2";
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+		opp-shared;
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+
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+		opp-312000000 {
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+			opp-hz = /bits/ 64 <312000000>;
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+			opp-microvolt = <875000>;
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+			clock-latency-ns = <40000>;
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+		};
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+		opp-504000000 {
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+			opp-hz = /bits/ 64 <504000000>;
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+			opp-microvolt = <925000>;
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+		};
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+		opp-600000000 {
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+			opp-hz = /bits/ 64 <600000000>;
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+			opp-microvolt = <950000>;
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+			opp-suspend;
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+		};
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+		opp-816000000 {
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+			opp-hz = /bits/ 64 <816000000>;
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+			opp-microvolt = <975000>;
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+		};
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+		opp-1008000000 {
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+			opp-hz = /bits/ 64 <1008000000>;
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+			opp-microvolt = <1075000>;
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+		};
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+		opp-1200000000 {
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+			opp-hz = /bits/ 64 <1200000000>;
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+			opp-microvolt = <1150000>;
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+		};
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+		opp-1416000000 {
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+			opp-hz = /bits/ 64 <1416000000>;
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+			opp-microvolt = <1250000>;
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+		};
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+		opp-1608000000 {
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+			opp-hz = /bits/ 64 <1608000000>;
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+			opp-microvolt = <1350000>;
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+		};
102
+	};
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+
104
+	display-subsystem {
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+		compatible = "rockchip,display-subsystem";
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+		ports = <&vop0_out>, <&vop1_out>;
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 	};
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108
 
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 	sram: sram@10080000 {
..
..
@@ -66,6 +116,40 @@
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 		smp-sram@0 {
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 			compatible = "rockchip,rk3066-smp-sram";
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 			reg = <0x0 0x50>;
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+		};
120
+	};
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+
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+	vop0: vop@1010c000 {
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+		compatible = "rockchip,rk3188-vop";
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+		reg = <0x1010c000 0x1000>;
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+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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+		clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
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+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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+		power-domains = <&power RK3188_PD_VIO>;
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+		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
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+		reset-names = "axi", "ahb", "dclk";
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+		status = "disabled";
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+
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+		vop0_out: port {
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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+		};
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+	};
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+
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+	vop1: vop@1010e000 {
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+		compatible = "rockchip,rk3188-vop";
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+		reg = <0x1010e000 0x1000>;
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+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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+		clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
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+		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
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+		power-domains = <&power RK3188_PD_VIO>;
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+		resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
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+		reset-names = "axi", "ahb", "dclk";
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+		status = "disabled";
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+
150
+		vop1_out: port {
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+			#address-cells = <1>;
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+			#size-cells = <0>;
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 		};
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 	};
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155
 
..
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@@ -89,8 +173,6 @@
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 		compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
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 		reg = <0x1011a000 0x2000>;
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 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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-		#address-cells = <1>;
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-		#size-cells = <0>;
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 		pinctrl-names = "default";
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 		pinctrl-0 = <&i2s0_bus>;
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 		dmas = <&dmac1_s 6>, <&dmac1_s 7>;
..
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@@ -99,6 +181,7 @@
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 		clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S0>;
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 		rockchip,playback-channels = <2>;
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 		rockchip,capture-channels = <2>;
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+		#sound-dai-cells = <0>;
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 		status = "disabled";
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 	};
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187
 
..
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@@ -106,8 +189,8 @@
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 		compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
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 		reg = <0x1011e000 0x2000>;
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 		#sound-dai-cells = <0>;
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-		clock-names = "hclk", "mclk";
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-		clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
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+		clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
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+		clock-names = "mclk", "hclk";
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 		dmas = <&dmac1_s 8>;
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 		dma-names = "tx";
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 		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
..
..
@@ -175,6 +258,7 @@
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 			compatible = "rockchip,rk3188-gpio-bank0";
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 			reg = <0x2000a000 0x100>;
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 			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO0>;
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263
 
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 			gpio-controller;
..
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@@ -188,6 +272,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x2003c000 0x100>;
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 			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO1>;
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277
 
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 			gpio-controller;
..
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@@ -201,6 +286,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x2003e000 0x100>;
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 			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO2>;
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291
 
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 			gpio-controller;
..
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@@ -214,6 +300,7 @@
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 			compatible = "rockchip,gpio-bank";
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 			reg = <0x20080000 0x100>;
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 			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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+			clock-names = "bus";
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 			clocks = <&cru PCLK_GPIO3>;
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305
 
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 			gpio-controller;
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@@ -306,6 +393,51 @@
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 			i2c4_xfer: i2c4-xfer {
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 				rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
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 						<1 RK_PD7 1 &pcfg_pull_none>;
396
+			};
397
+		};
398
+
399
+		lcdc1 {
400
+			lcdc1_dclk: lcdc1-dclk {
401
+				rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
402
+			};
403
+
404
+			lcdc1_den: lcdc1-den {
405
+				rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
406
+			};
407
+
408
+			lcdc1_hsync: lcdc1-hsync {
409
+				rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
410
+			};
411
+
412
+			lcdc1_vsync: lcdc1-vsync {
413
+				rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
414
+			};
415
+
416
+			lcdc1_rgb24: lcdc1-rgb24 {
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+				rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
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+						<2 RK_PA1 1 &pcfg_pull_none>,
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+						<2 RK_PA2 1 &pcfg_pull_none>,
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+						<2 RK_PA3 1 &pcfg_pull_none>,
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+						<2 RK_PA4 1 &pcfg_pull_none>,
422
+						<2 RK_PA5 1 &pcfg_pull_none>,
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+						<2 RK_PA6 1 &pcfg_pull_none>,
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+						<2 RK_PA7 1 &pcfg_pull_none>,
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+						<2 RK_PB0 1 &pcfg_pull_none>,
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+						<2 RK_PB1 1 &pcfg_pull_none>,
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+						<2 RK_PB2 1 &pcfg_pull_none>,
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+						<2 RK_PB3 1 &pcfg_pull_none>,
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+						<2 RK_PB4 1 &pcfg_pull_none>,
430
+						<2 RK_PB5 1 &pcfg_pull_none>,
431
+						<2 RK_PB6 1 &pcfg_pull_none>,
432
+						<2 RK_PB7 1 &pcfg_pull_none>,
433
+						<2 RK_PC0 1 &pcfg_pull_none>,
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+						<2 RK_PC1 1 &pcfg_pull_none>,
435
+						<2 RK_PC2 1 &pcfg_pull_none>,
436
+						<2 RK_PC3 1 &pcfg_pull_none>,
437
+						<2 RK_PC4 1 &pcfg_pull_none>,
438
+						<2 RK_PC5 1 &pcfg_pull_none>,
439
+						<2 RK_PC6 1 &pcfg_pull_none>,
440
+						<2 RK_PC7 1 &pcfg_pull_none>;
309
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 			};
310
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 		};
311
443
 
..
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@@ -509,7 +641,6 @@
509
641
 
510
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 &global_timer {
511
643
 	interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
512
-	status = "disabled";
513
644
 };
514
645
 
515
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 &local_timer {
..
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@@ -538,6 +669,7 @@
538
669
 			  "ppmmu2",
539
670
 			  "pp3",
540
671
 			  "ppmmu3";
672
+	power-domains = <&power RK3188_PD_GPU>;
541
673
 };
542
674
 
543
675
 &i2c0 {
..
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@@ -570,6 +702,52 @@
570
702
 	pinctrl-0 = <&i2c4_xfer>;
571
703
 };
572
704
 
705
+&pmu {
706
+	power: power-controller {
707
+		compatible = "rockchip,rk3188-power-controller";
708
+		#power-domain-cells = <1>;
709
+		#address-cells = <1>;
710
+		#size-cells = <0>;
711
+
712
+		power-domain@RK3188_PD_VIO {
713
+			reg = <RK3188_PD_VIO>;
714
+			clocks = <&cru ACLK_LCDC0>,
715
+				 <&cru ACLK_LCDC1>,
716
+				 <&cru DCLK_LCDC0>,
717
+				 <&cru DCLK_LCDC1>,
718
+				 <&cru HCLK_LCDC0>,
719
+				 <&cru HCLK_LCDC1>,
720
+				 <&cru SCLK_CIF0>,
721
+				 <&cru ACLK_CIF0>,
722
+				 <&cru HCLK_CIF0>,
723
+				 <&cru ACLK_IPP>,
724
+				 <&cru HCLK_IPP>,
725
+				 <&cru ACLK_RGA>,
726
+				 <&cru HCLK_RGA>;
727
+			pm_qos = <&qos_lcdc0>,
728
+				 <&qos_lcdc1>,
729
+				 <&qos_cif0>,
730
+				 <&qos_ipp>,
731
+				 <&qos_rga>;
732
+		};
733
+
734
+		power-domain@RK3188_PD_VIDEO {
735
+			reg = <RK3188_PD_VIDEO>;
736
+			clocks = <&cru ACLK_VDPU>,
737
+				 <&cru ACLK_VEPU>,
738
+				 <&cru HCLK_VDPU>,
739
+				 <&cru HCLK_VEPU>;
740
+			pm_qos = <&qos_vpu>;
741
+		};
742
+
743
+		power-domain@RK3188_PD_GPU {
744
+			reg = <RK3188_PD_GPU>;
745
+			clocks = <&cru ACLK_GPU>;
746
+			pm_qos = <&qos_gpu>;
747
+		};
748
+	};
749
+};
750
+
573
751
 &pwm0 {
574
752
 	pinctrl-names = "active";
575
753
 	pinctrl-0 = <&pwm0_out>;