.. | .. |
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7 | 7 | #include <dt-bindings/gpio/gpio.h> |
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8 | 8 | #include <dt-bindings/pinctrl/rockchip.h> |
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9 | 9 | #include <dt-bindings/clock/rk3188-cru.h> |
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| 10 | +#include <dt-bindings/power/rk3188-power.h> |
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10 | 11 | #include "rk3xxx.dtsi" |
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11 | 12 | |
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12 | 13 | / { |
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13 | 14 | compatible = "rockchip,rk3188"; |
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| 15 | + |
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| 16 | + aliases { |
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| 17 | + gpio0 = &gpio0; |
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| 18 | + gpio1 = &gpio1; |
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| 19 | + gpio2 = &gpio2; |
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| 20 | + gpio3 = &gpio3; |
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| 21 | + }; |
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14 | 22 | |
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15 | 23 | cpus { |
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16 | 24 | #address-cells = <1>; |
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.. | .. |
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22 | 30 | compatible = "arm,cortex-a9"; |
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23 | 31 | next-level-cache = <&L2>; |
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24 | 32 | reg = <0x0>; |
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25 | | - operating-points = < |
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26 | | - /* kHz uV */ |
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27 | | - 1608000 1350000 |
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28 | | - 1416000 1250000 |
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29 | | - 1200000 1150000 |
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30 | | - 1008000 1075000 |
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31 | | - 816000 975000 |
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32 | | - 600000 950000 |
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33 | | - 504000 925000 |
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34 | | - 312000 875000 |
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35 | | - >; |
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36 | 33 | clock-latency = <40000>; |
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37 | 34 | clocks = <&cru ARMCLK>; |
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| 35 | + operating-points-v2 = <&cpu0_opp_table>; |
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| 36 | + resets = <&cru SRST_CORE0>; |
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38 | 37 | }; |
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39 | | - cpu@1 { |
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| 38 | + cpu1: cpu@1 { |
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40 | 39 | device_type = "cpu"; |
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41 | 40 | compatible = "arm,cortex-a9"; |
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42 | 41 | next-level-cache = <&L2>; |
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43 | 42 | reg = <0x1>; |
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| 43 | + operating-points-v2 = <&cpu0_opp_table>; |
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| 44 | + resets = <&cru SRST_CORE1>; |
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44 | 45 | }; |
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45 | | - cpu@2 { |
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| 46 | + cpu2: cpu@2 { |
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46 | 47 | device_type = "cpu"; |
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47 | 48 | compatible = "arm,cortex-a9"; |
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48 | 49 | next-level-cache = <&L2>; |
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49 | 50 | reg = <0x2>; |
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| 51 | + operating-points-v2 = <&cpu0_opp_table>; |
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| 52 | + resets = <&cru SRST_CORE2>; |
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50 | 53 | }; |
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51 | | - cpu@3 { |
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| 54 | + cpu3: cpu@3 { |
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52 | 55 | device_type = "cpu"; |
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53 | 56 | compatible = "arm,cortex-a9"; |
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54 | 57 | next-level-cache = <&L2>; |
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55 | 58 | reg = <0x3>; |
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| 59 | + operating-points-v2 = <&cpu0_opp_table>; |
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| 60 | + resets = <&cru SRST_CORE3>; |
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56 | 61 | }; |
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| 62 | + }; |
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| 63 | + |
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| 64 | + cpu0_opp_table: opp_table0 { |
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| 65 | + compatible = "operating-points-v2"; |
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| 66 | + opp-shared; |
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| 67 | + |
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| 68 | + opp-312000000 { |
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| 69 | + opp-hz = /bits/ 64 <312000000>; |
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| 70 | + opp-microvolt = <875000>; |
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| 71 | + clock-latency-ns = <40000>; |
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| 72 | + }; |
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| 73 | + opp-504000000 { |
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| 74 | + opp-hz = /bits/ 64 <504000000>; |
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| 75 | + opp-microvolt = <925000>; |
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| 76 | + }; |
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| 77 | + opp-600000000 { |
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| 78 | + opp-hz = /bits/ 64 <600000000>; |
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| 79 | + opp-microvolt = <950000>; |
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| 80 | + opp-suspend; |
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| 81 | + }; |
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| 82 | + opp-816000000 { |
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| 83 | + opp-hz = /bits/ 64 <816000000>; |
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| 84 | + opp-microvolt = <975000>; |
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| 85 | + }; |
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| 86 | + opp-1008000000 { |
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| 87 | + opp-hz = /bits/ 64 <1008000000>; |
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| 88 | + opp-microvolt = <1075000>; |
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| 89 | + }; |
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| 90 | + opp-1200000000 { |
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| 91 | + opp-hz = /bits/ 64 <1200000000>; |
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| 92 | + opp-microvolt = <1150000>; |
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| 93 | + }; |
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| 94 | + opp-1416000000 { |
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| 95 | + opp-hz = /bits/ 64 <1416000000>; |
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| 96 | + opp-microvolt = <1250000>; |
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| 97 | + }; |
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| 98 | + opp-1608000000 { |
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| 99 | + opp-hz = /bits/ 64 <1608000000>; |
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| 100 | + opp-microvolt = <1350000>; |
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| 101 | + }; |
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| 102 | + }; |
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| 103 | + |
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| 104 | + display-subsystem { |
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| 105 | + compatible = "rockchip,display-subsystem"; |
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| 106 | + ports = <&vop0_out>, <&vop1_out>; |
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57 | 107 | }; |
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58 | 108 | |
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59 | 109 | sram: sram@10080000 { |
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.. | .. |
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66 | 116 | smp-sram@0 { |
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67 | 117 | compatible = "rockchip,rk3066-smp-sram"; |
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68 | 118 | reg = <0x0 0x50>; |
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| 119 | + }; |
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| 120 | + }; |
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| 121 | + |
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| 122 | + vop0: vop@1010c000 { |
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| 123 | + compatible = "rockchip,rk3188-vop"; |
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| 124 | + reg = <0x1010c000 0x1000>; |
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| 125 | + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
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| 126 | + clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>; |
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| 127 | + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; |
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| 128 | + power-domains = <&power RK3188_PD_VIO>; |
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| 129 | + resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>; |
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| 130 | + reset-names = "axi", "ahb", "dclk"; |
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| 131 | + status = "disabled"; |
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| 132 | + |
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| 133 | + vop0_out: port { |
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| 134 | + #address-cells = <1>; |
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| 135 | + #size-cells = <0>; |
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| 136 | + }; |
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| 137 | + }; |
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| 138 | + |
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| 139 | + vop1: vop@1010e000 { |
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| 140 | + compatible = "rockchip,rk3188-vop"; |
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| 141 | + reg = <0x1010e000 0x1000>; |
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| 142 | + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
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| 143 | + clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>; |
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| 144 | + clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; |
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| 145 | + power-domains = <&power RK3188_PD_VIO>; |
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| 146 | + resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>; |
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| 147 | + reset-names = "axi", "ahb", "dclk"; |
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| 148 | + status = "disabled"; |
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| 149 | + |
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| 150 | + vop1_out: port { |
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| 151 | + #address-cells = <1>; |
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| 152 | + #size-cells = <0>; |
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69 | 153 | }; |
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70 | 154 | }; |
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71 | 155 | |
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.. | .. |
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89 | 173 | compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; |
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90 | 174 | reg = <0x1011a000 0x2000>; |
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91 | 175 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
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92 | | - #address-cells = <1>; |
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93 | | - #size-cells = <0>; |
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94 | 176 | pinctrl-names = "default"; |
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95 | 177 | pinctrl-0 = <&i2s0_bus>; |
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96 | 178 | dmas = <&dmac1_s 6>, <&dmac1_s 7>; |
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.. | .. |
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99 | 181 | clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S0>; |
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100 | 182 | rockchip,playback-channels = <2>; |
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101 | 183 | rockchip,capture-channels = <2>; |
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| 184 | + #sound-dai-cells = <0>; |
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102 | 185 | status = "disabled"; |
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103 | 186 | }; |
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104 | 187 | |
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.. | .. |
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106 | 189 | compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif"; |
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107 | 190 | reg = <0x1011e000 0x2000>; |
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108 | 191 | #sound-dai-cells = <0>; |
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109 | | - clock-names = "hclk", "mclk"; |
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110 | | - clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>; |
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| 192 | + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; |
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| 193 | + clock-names = "mclk", "hclk"; |
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111 | 194 | dmas = <&dmac1_s 8>; |
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112 | 195 | dma-names = "tx"; |
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113 | 196 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
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.. | .. |
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175 | 258 | compatible = "rockchip,rk3188-gpio-bank0"; |
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176 | 259 | reg = <0x2000a000 0x100>; |
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177 | 260 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; |
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| 261 | + clock-names = "bus"; |
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178 | 262 | clocks = <&cru PCLK_GPIO0>; |
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179 | 263 | |
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180 | 264 | gpio-controller; |
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.. | .. |
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188 | 272 | compatible = "rockchip,gpio-bank"; |
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189 | 273 | reg = <0x2003c000 0x100>; |
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190 | 274 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
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| 275 | + clock-names = "bus"; |
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191 | 276 | clocks = <&cru PCLK_GPIO1>; |
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192 | 277 | |
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193 | 278 | gpio-controller; |
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.. | .. |
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201 | 286 | compatible = "rockchip,gpio-bank"; |
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202 | 287 | reg = <0x2003e000 0x100>; |
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203 | 288 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
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| 289 | + clock-names = "bus"; |
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204 | 290 | clocks = <&cru PCLK_GPIO2>; |
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205 | 291 | |
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206 | 292 | gpio-controller; |
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.. | .. |
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214 | 300 | compatible = "rockchip,gpio-bank"; |
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215 | 301 | reg = <0x20080000 0x100>; |
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216 | 302 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
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| 303 | + clock-names = "bus"; |
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217 | 304 | clocks = <&cru PCLK_GPIO3>; |
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218 | 305 | |
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219 | 306 | gpio-controller; |
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.. | .. |
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306 | 393 | i2c4_xfer: i2c4-xfer { |
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307 | 394 | rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>, |
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308 | 395 | <1 RK_PD7 1 &pcfg_pull_none>; |
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| 396 | + }; |
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| 397 | + }; |
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| 398 | + |
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| 399 | + lcdc1 { |
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| 400 | + lcdc1_dclk: lcdc1-dclk { |
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| 401 | + rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>; |
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| 402 | + }; |
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| 403 | + |
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| 404 | + lcdc1_den: lcdc1-den { |
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| 405 | + rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>; |
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| 406 | + }; |
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| 407 | + |
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| 408 | + lcdc1_hsync: lcdc1-hsync { |
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| 409 | + rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; |
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| 410 | + }; |
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| 411 | + |
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| 412 | + lcdc1_vsync: lcdc1-vsync { |
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| 413 | + rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; |
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| 414 | + }; |
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| 415 | + |
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| 416 | + lcdc1_rgb24: lcdc1-rgb24 { |
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| 417 | + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>, |
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| 418 | + <2 RK_PA1 1 &pcfg_pull_none>, |
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| 419 | + <2 RK_PA2 1 &pcfg_pull_none>, |
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| 420 | + <2 RK_PA3 1 &pcfg_pull_none>, |
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| 421 | + <2 RK_PA4 1 &pcfg_pull_none>, |
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| 422 | + <2 RK_PA5 1 &pcfg_pull_none>, |
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| 423 | + <2 RK_PA6 1 &pcfg_pull_none>, |
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| 424 | + <2 RK_PA7 1 &pcfg_pull_none>, |
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| 425 | + <2 RK_PB0 1 &pcfg_pull_none>, |
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| 426 | + <2 RK_PB1 1 &pcfg_pull_none>, |
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| 427 | + <2 RK_PB2 1 &pcfg_pull_none>, |
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| 428 | + <2 RK_PB3 1 &pcfg_pull_none>, |
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| 429 | + <2 RK_PB4 1 &pcfg_pull_none>, |
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| 430 | + <2 RK_PB5 1 &pcfg_pull_none>, |
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| 431 | + <2 RK_PB6 1 &pcfg_pull_none>, |
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| 432 | + <2 RK_PB7 1 &pcfg_pull_none>, |
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| 433 | + <2 RK_PC0 1 &pcfg_pull_none>, |
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| 434 | + <2 RK_PC1 1 &pcfg_pull_none>, |
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| 435 | + <2 RK_PC2 1 &pcfg_pull_none>, |
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| 436 | + <2 RK_PC3 1 &pcfg_pull_none>, |
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| 437 | + <2 RK_PC4 1 &pcfg_pull_none>, |
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| 438 | + <2 RK_PC5 1 &pcfg_pull_none>, |
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| 439 | + <2 RK_PC6 1 &pcfg_pull_none>, |
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| 440 | + <2 RK_PC7 1 &pcfg_pull_none>; |
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309 | 441 | }; |
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310 | 442 | }; |
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311 | 443 | |
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.. | .. |
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509 | 641 | |
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510 | 642 | &global_timer { |
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511 | 643 | interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; |
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512 | | - status = "disabled"; |
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513 | 644 | }; |
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514 | 645 | |
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515 | 646 | &local_timer { |
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.. | .. |
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538 | 669 | "ppmmu2", |
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539 | 670 | "pp3", |
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540 | 671 | "ppmmu3"; |
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| 672 | + power-domains = <&power RK3188_PD_GPU>; |
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541 | 673 | }; |
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542 | 674 | |
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543 | 675 | &i2c0 { |
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.. | .. |
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570 | 702 | pinctrl-0 = <&i2c4_xfer>; |
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571 | 703 | }; |
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572 | 704 | |
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| 705 | +&pmu { |
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| 706 | + power: power-controller { |
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| 707 | + compatible = "rockchip,rk3188-power-controller"; |
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| 708 | + #power-domain-cells = <1>; |
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| 709 | + #address-cells = <1>; |
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| 710 | + #size-cells = <0>; |
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| 711 | + |
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| 712 | + power-domain@RK3188_PD_VIO { |
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| 713 | + reg = <RK3188_PD_VIO>; |
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| 714 | + clocks = <&cru ACLK_LCDC0>, |
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| 715 | + <&cru ACLK_LCDC1>, |
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| 716 | + <&cru DCLK_LCDC0>, |
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| 717 | + <&cru DCLK_LCDC1>, |
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| 718 | + <&cru HCLK_LCDC0>, |
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| 719 | + <&cru HCLK_LCDC1>, |
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| 720 | + <&cru SCLK_CIF0>, |
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| 721 | + <&cru ACLK_CIF0>, |
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| 722 | + <&cru HCLK_CIF0>, |
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| 723 | + <&cru ACLK_IPP>, |
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| 724 | + <&cru HCLK_IPP>, |
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| 725 | + <&cru ACLK_RGA>, |
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| 726 | + <&cru HCLK_RGA>; |
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| 727 | + pm_qos = <&qos_lcdc0>, |
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| 728 | + <&qos_lcdc1>, |
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| 729 | + <&qos_cif0>, |
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| 730 | + <&qos_ipp>, |
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| 731 | + <&qos_rga>; |
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| 732 | + }; |
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| 733 | + |
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| 734 | + power-domain@RK3188_PD_VIDEO { |
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| 735 | + reg = <RK3188_PD_VIDEO>; |
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| 736 | + clocks = <&cru ACLK_VDPU>, |
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| 737 | + <&cru ACLK_VEPU>, |
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| 738 | + <&cru HCLK_VDPU>, |
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| 739 | + <&cru HCLK_VEPU>; |
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| 740 | + pm_qos = <&qos_vpu>; |
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| 741 | + }; |
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| 742 | + |
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| 743 | + power-domain@RK3188_PD_GPU { |
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| 744 | + reg = <RK3188_PD_GPU>; |
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| 745 | + clocks = <&cru ACLK_GPU>; |
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| 746 | + pm_qos = <&qos_gpu>; |
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| 747 | + }; |
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| 748 | + }; |
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| 749 | +}; |
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| 750 | + |
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573 | 751 | &pwm0 { |
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574 | 752 | pinctrl-names = "active"; |
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575 | 753 | pinctrl-0 = <&pwm0_out>; |
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