hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/arm/boot/dts/rk3188.dtsi
....@@ -7,10 +7,18 @@
77 #include <dt-bindings/gpio/gpio.h>
88 #include <dt-bindings/pinctrl/rockchip.h>
99 #include <dt-bindings/clock/rk3188-cru.h>
10
+#include <dt-bindings/power/rk3188-power.h>
1011 #include "rk3xxx.dtsi"
1112
1213 / {
1314 compatible = "rockchip,rk3188";
15
+
16
+ aliases {
17
+ gpio0 = &gpio0;
18
+ gpio1 = &gpio1;
19
+ gpio2 = &gpio2;
20
+ gpio3 = &gpio3;
21
+ };
1422
1523 cpus {
1624 #address-cells = <1>;
....@@ -22,38 +30,80 @@
2230 compatible = "arm,cortex-a9";
2331 next-level-cache = <&L2>;
2432 reg = <0x0>;
25
- operating-points = <
26
- /* kHz uV */
27
- 1608000 1350000
28
- 1416000 1250000
29
- 1200000 1150000
30
- 1008000 1075000
31
- 816000 975000
32
- 600000 950000
33
- 504000 925000
34
- 312000 875000
35
- >;
3633 clock-latency = <40000>;
3734 clocks = <&cru ARMCLK>;
35
+ operating-points-v2 = <&cpu0_opp_table>;
36
+ resets = <&cru SRST_CORE0>;
3837 };
39
- cpu@1 {
38
+ cpu1: cpu@1 {
4039 device_type = "cpu";
4140 compatible = "arm,cortex-a9";
4241 next-level-cache = <&L2>;
4342 reg = <0x1>;
43
+ operating-points-v2 = <&cpu0_opp_table>;
44
+ resets = <&cru SRST_CORE1>;
4445 };
45
- cpu@2 {
46
+ cpu2: cpu@2 {
4647 device_type = "cpu";
4748 compatible = "arm,cortex-a9";
4849 next-level-cache = <&L2>;
4950 reg = <0x2>;
51
+ operating-points-v2 = <&cpu0_opp_table>;
52
+ resets = <&cru SRST_CORE2>;
5053 };
51
- cpu@3 {
54
+ cpu3: cpu@3 {
5255 device_type = "cpu";
5356 compatible = "arm,cortex-a9";
5457 next-level-cache = <&L2>;
5558 reg = <0x3>;
59
+ operating-points-v2 = <&cpu0_opp_table>;
60
+ resets = <&cru SRST_CORE3>;
5661 };
62
+ };
63
+
64
+ cpu0_opp_table: opp_table0 {
65
+ compatible = "operating-points-v2";
66
+ opp-shared;
67
+
68
+ opp-312000000 {
69
+ opp-hz = /bits/ 64 <312000000>;
70
+ opp-microvolt = <875000>;
71
+ clock-latency-ns = <40000>;
72
+ };
73
+ opp-504000000 {
74
+ opp-hz = /bits/ 64 <504000000>;
75
+ opp-microvolt = <925000>;
76
+ };
77
+ opp-600000000 {
78
+ opp-hz = /bits/ 64 <600000000>;
79
+ opp-microvolt = <950000>;
80
+ opp-suspend;
81
+ };
82
+ opp-816000000 {
83
+ opp-hz = /bits/ 64 <816000000>;
84
+ opp-microvolt = <975000>;
85
+ };
86
+ opp-1008000000 {
87
+ opp-hz = /bits/ 64 <1008000000>;
88
+ opp-microvolt = <1075000>;
89
+ };
90
+ opp-1200000000 {
91
+ opp-hz = /bits/ 64 <1200000000>;
92
+ opp-microvolt = <1150000>;
93
+ };
94
+ opp-1416000000 {
95
+ opp-hz = /bits/ 64 <1416000000>;
96
+ opp-microvolt = <1250000>;
97
+ };
98
+ opp-1608000000 {
99
+ opp-hz = /bits/ 64 <1608000000>;
100
+ opp-microvolt = <1350000>;
101
+ };
102
+ };
103
+
104
+ display-subsystem {
105
+ compatible = "rockchip,display-subsystem";
106
+ ports = <&vop0_out>, <&vop1_out>;
57107 };
58108
59109 sram: sram@10080000 {
....@@ -66,6 +116,40 @@
66116 smp-sram@0 {
67117 compatible = "rockchip,rk3066-smp-sram";
68118 reg = <0x0 0x50>;
119
+ };
120
+ };
121
+
122
+ vop0: vop@1010c000 {
123
+ compatible = "rockchip,rk3188-vop";
124
+ reg = <0x1010c000 0x1000>;
125
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
126
+ clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
127
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
128
+ power-domains = <&power RK3188_PD_VIO>;
129
+ resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
130
+ reset-names = "axi", "ahb", "dclk";
131
+ status = "disabled";
132
+
133
+ vop0_out: port {
134
+ #address-cells = <1>;
135
+ #size-cells = <0>;
136
+ };
137
+ };
138
+
139
+ vop1: vop@1010e000 {
140
+ compatible = "rockchip,rk3188-vop";
141
+ reg = <0x1010e000 0x1000>;
142
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
143
+ clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
144
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
145
+ power-domains = <&power RK3188_PD_VIO>;
146
+ resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
147
+ reset-names = "axi", "ahb", "dclk";
148
+ status = "disabled";
149
+
150
+ vop1_out: port {
151
+ #address-cells = <1>;
152
+ #size-cells = <0>;
69153 };
70154 };
71155
....@@ -89,8 +173,6 @@
89173 compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
90174 reg = <0x1011a000 0x2000>;
91175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
92
- #address-cells = <1>;
93
- #size-cells = <0>;
94176 pinctrl-names = "default";
95177 pinctrl-0 = <&i2s0_bus>;
96178 dmas = <&dmac1_s 6>, <&dmac1_s 7>;
....@@ -99,6 +181,7 @@
99181 clocks = <&cru HCLK_I2S0_2CH>, <&cru SCLK_I2S0>;
100182 rockchip,playback-channels = <2>;
101183 rockchip,capture-channels = <2>;
184
+ #sound-dai-cells = <0>;
102185 status = "disabled";
103186 };
104187
....@@ -106,8 +189,8 @@
106189 compatible = "rockchip,rk3188-spdif", "rockchip,rk3066-spdif";
107190 reg = <0x1011e000 0x2000>;
108191 #sound-dai-cells = <0>;
109
- clock-names = "hclk", "mclk";
110
- clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF>;
192
+ clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>;
193
+ clock-names = "mclk", "hclk";
111194 dmas = <&dmac1_s 8>;
112195 dma-names = "tx";
113196 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
....@@ -175,6 +258,7 @@
175258 compatible = "rockchip,rk3188-gpio-bank0";
176259 reg = <0x2000a000 0x100>;
177260 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
261
+ clock-names = "bus";
178262 clocks = <&cru PCLK_GPIO0>;
179263
180264 gpio-controller;
....@@ -188,6 +272,7 @@
188272 compatible = "rockchip,gpio-bank";
189273 reg = <0x2003c000 0x100>;
190274 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
275
+ clock-names = "bus";
191276 clocks = <&cru PCLK_GPIO1>;
192277
193278 gpio-controller;
....@@ -201,6 +286,7 @@
201286 compatible = "rockchip,gpio-bank";
202287 reg = <0x2003e000 0x100>;
203288 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
289
+ clock-names = "bus";
204290 clocks = <&cru PCLK_GPIO2>;
205291
206292 gpio-controller;
....@@ -214,6 +300,7 @@
214300 compatible = "rockchip,gpio-bank";
215301 reg = <0x20080000 0x100>;
216302 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
303
+ clock-names = "bus";
217304 clocks = <&cru PCLK_GPIO3>;
218305
219306 gpio-controller;
....@@ -306,6 +393,51 @@
306393 i2c4_xfer: i2c4-xfer {
307394 rockchip,pins = <1 RK_PD6 1 &pcfg_pull_none>,
308395 <1 RK_PD7 1 &pcfg_pull_none>;
396
+ };
397
+ };
398
+
399
+ lcdc1 {
400
+ lcdc1_dclk: lcdc1-dclk {
401
+ rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>;
402
+ };
403
+
404
+ lcdc1_den: lcdc1-den {
405
+ rockchip,pins = <2 RK_PD1 1 &pcfg_pull_none>;
406
+ };
407
+
408
+ lcdc1_hsync: lcdc1-hsync {
409
+ rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
410
+ };
411
+
412
+ lcdc1_vsync: lcdc1-vsync {
413
+ rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
414
+ };
415
+
416
+ lcdc1_rgb24: lcdc1-rgb24 {
417
+ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>,
418
+ <2 RK_PA1 1 &pcfg_pull_none>,
419
+ <2 RK_PA2 1 &pcfg_pull_none>,
420
+ <2 RK_PA3 1 &pcfg_pull_none>,
421
+ <2 RK_PA4 1 &pcfg_pull_none>,
422
+ <2 RK_PA5 1 &pcfg_pull_none>,
423
+ <2 RK_PA6 1 &pcfg_pull_none>,
424
+ <2 RK_PA7 1 &pcfg_pull_none>,
425
+ <2 RK_PB0 1 &pcfg_pull_none>,
426
+ <2 RK_PB1 1 &pcfg_pull_none>,
427
+ <2 RK_PB2 1 &pcfg_pull_none>,
428
+ <2 RK_PB3 1 &pcfg_pull_none>,
429
+ <2 RK_PB4 1 &pcfg_pull_none>,
430
+ <2 RK_PB5 1 &pcfg_pull_none>,
431
+ <2 RK_PB6 1 &pcfg_pull_none>,
432
+ <2 RK_PB7 1 &pcfg_pull_none>,
433
+ <2 RK_PC0 1 &pcfg_pull_none>,
434
+ <2 RK_PC1 1 &pcfg_pull_none>,
435
+ <2 RK_PC2 1 &pcfg_pull_none>,
436
+ <2 RK_PC3 1 &pcfg_pull_none>,
437
+ <2 RK_PC4 1 &pcfg_pull_none>,
438
+ <2 RK_PC5 1 &pcfg_pull_none>,
439
+ <2 RK_PC6 1 &pcfg_pull_none>,
440
+ <2 RK_PC7 1 &pcfg_pull_none>;
309441 };
310442 };
311443
....@@ -509,7 +641,6 @@
509641
510642 &global_timer {
511643 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
512
- status = "disabled";
513644 };
514645
515646 &local_timer {
....@@ -538,6 +669,7 @@
538669 "ppmmu2",
539670 "pp3",
540671 "ppmmu3";
672
+ power-domains = <&power RK3188_PD_GPU>;
541673 };
542674
543675 &i2c0 {
....@@ -570,6 +702,52 @@
570702 pinctrl-0 = <&i2c4_xfer>;
571703 };
572704
705
+&pmu {
706
+ power: power-controller {
707
+ compatible = "rockchip,rk3188-power-controller";
708
+ #power-domain-cells = <1>;
709
+ #address-cells = <1>;
710
+ #size-cells = <0>;
711
+
712
+ power-domain@RK3188_PD_VIO {
713
+ reg = <RK3188_PD_VIO>;
714
+ clocks = <&cru ACLK_LCDC0>,
715
+ <&cru ACLK_LCDC1>,
716
+ <&cru DCLK_LCDC0>,
717
+ <&cru DCLK_LCDC1>,
718
+ <&cru HCLK_LCDC0>,
719
+ <&cru HCLK_LCDC1>,
720
+ <&cru SCLK_CIF0>,
721
+ <&cru ACLK_CIF0>,
722
+ <&cru HCLK_CIF0>,
723
+ <&cru ACLK_IPP>,
724
+ <&cru HCLK_IPP>,
725
+ <&cru ACLK_RGA>,
726
+ <&cru HCLK_RGA>;
727
+ pm_qos = <&qos_lcdc0>,
728
+ <&qos_lcdc1>,
729
+ <&qos_cif0>,
730
+ <&qos_ipp>,
731
+ <&qos_rga>;
732
+ };
733
+
734
+ power-domain@RK3188_PD_VIDEO {
735
+ reg = <RK3188_PD_VIDEO>;
736
+ clocks = <&cru ACLK_VDPU>,
737
+ <&cru ACLK_VEPU>,
738
+ <&cru HCLK_VDPU>,
739
+ <&cru HCLK_VEPU>;
740
+ pm_qos = <&qos_vpu>;
741
+ };
742
+
743
+ power-domain@RK3188_PD_GPU {
744
+ reg = <RK3188_PD_GPU>;
745
+ clocks = <&cru ACLK_GPU>;
746
+ pm_qos = <&qos_gpu>;
747
+ };
748
+ };
749
+};
750
+
573751 &pwm0 {
574752 pinctrl-names = "active";
575753 pinctrl-0 = <&pwm0_out>;