add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/rk312x.dtsi
..
..
@@ -57,9 +57,6 @@
57
57
 
58
58
 	aliases {
59
59
 		ethernet0 = &gmac;
60
-		serial0 = &uart0;
61
-		serial1 = &uart1;
62
-		serial2 = &uart2;
63
60
 		i2c0 = &i2c0;
64
61
 		i2c1 = &i2c1;
65
62
 		i2c2 = &i2c2;
..
..
@@ -67,6 +64,10 @@
67
64
 		mmc0 = &sdmmc;
68
65
 		mmc1 = &sdio;
69
66
 		mmc2 = &emmc;
67
+		serial0 = &uart0;
68
+		serial1 = &uart1;
69
+		serial2 = &uart2;
70
+		spi0 = &spi0;
70
71
 	};
71
72
 
72
73
 	cpus {
..
..
@@ -113,8 +114,8 @@
113
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 		clocks = <&cru PLL_APLL>;
114
115
 		rockchip,leakage-voltage-sel = <
115
116
 			1   13   0
116
-			14  18   1
117
-			18  254  2
117
+			14  49   1
118
+			50  254  2
118
119
 		>;
119
120
 		nvmem-cells = <&cpu_leakage>;
120
121
 		nvmem-cell-names = "cpu_leakage";
..
..
@@ -233,7 +234,7 @@
233
234
 		system-status-freq = <
234
235
 			/*system status		freq(KHz)*/
235
236
 			SYS_STATUS_NORMAL	456000
236
-			SYS_STATUS_SUSPEND	456000
237
+			SYS_STATUS_SUSPEND	300000
237
238
 			SYS_STATUS_REBOOT	456000
238
239
 		>;
239
240
 		auto-min-freq = <456000>;
..
..
@@ -247,6 +248,7 @@
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 		opp-200000000 {
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 			opp-hz = /bits/ 64 <200000000>;
249
250
 			opp-microvolt = <1025000>;
251
+			status = "disabled";
250
252
 		};
251
253
 		opp-300000000 {
252
254
 			opp-hz = /bits/ 64 <300000000>;
..
..
@@ -615,7 +617,6 @@
615
617
 		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
616
618
 		clock-names = "aclk_rga", "hclk_rga", "sclk_rga";
617
619
 		power-domains = <&power RK3128_PD_VIO>;
618
-		dma-coherent;
619
620
 		status = "disabled";
620
621
 	};
621
622
 
..
..
@@ -670,12 +671,12 @@
670
671
 		compatible = "rockchip,rk3128-mipi-dsi";
671
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 		reg = <0x10110000 0x4000>;
672
673
 		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
673
-		clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>;
674
-		clock-names = "pclk", "h2p", "hs_clk";
674
+		clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>;
675
+		clock-names = "pclk", "hclk";
675
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 		resets = <&cru SRST_VIO_MIPI_DSI>;
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677
 		reset-names = "apb";
677
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 		phys = <&video_phy>;
678
-		phy-names = "mipi_dphy";
679
+		phy-names = "dphy";
679
680
 		power-domains = <&power RK3128_PD_VIO>;
680
681
 		rockchip,grf = <&grf>;
681
682
 		#address-cells = <1>;
..
..
@@ -831,12 +832,11 @@
831
832
 		#size-cells = <0>;
832
833
 		pinctrl-names = "default";
833
834
 		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
834
-		clock-freq-min-max = <400000 50000000>;
835
-		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
836
-		clock-names = "biu", "ciu";
835
+		max-frequency = <50000000>;
836
+		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
837
+		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
837
838
 		dmas = <&pdma 10>;
838
839
 		dma-names = "rx-tx";
839
-		num-slots = <1>;
840
840
 		fifo-depth = <0x100>;
841
841
 		bus-width = <4>;
842
842
 		status = "disabled";
..
..
@@ -996,14 +996,15 @@
996
996
 	};
997
997
 
998
998
 	video_phy: video-phy@20038000 {
999
-		compatible = "rockchip,rk3128-video-phy";
999
+		compatible = "rockchip,rk3128-dsi-dphy", "rockchip,rk3128-video-phy";
1000
1000
 		reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
1001
+		reg-names = "phy", "host";
1001
1002
 		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>,
1002
1003
 			 <&cru PCLK_MIPI>;
1003
-		clock-names = "ref", "pclk_phy", "pclk_host";
1004
+		clock-names = "ref", "pclk", "pclk_host";
1004
1005
 		#clock-cells = <0>;
1005
1006
 		resets = <&cru SRST_MIPIPHY_P>;
1006
-		reset-names = "rst";
1007
+		reset-names = "apb";
1007
1008
 		power-domains = <&power RK3128_PD_VIO>;
1008
1009
 		#phy-cells = <0>;
1009
1010
 		status = "disabled";
..
..
@@ -1180,7 +1181,7 @@
1180
1181
 		reg = <0x20074000 0x1000>;
1181
1182
 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1182
1183
 		pinctrl-names = "default";
1183
-		pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
1184
+		pinctrl-0 = <&spi0m0_tx &spi0m0_rx &spi0m0_clk &spi0m0_cs0 &spi0m0_cs1>;
1184
1185
 		clock-names = "spiclk", "apb_pclk";
1185
1186
 		dmas = <&pdma 8>, <&pdma 9>;
1186
1187
 		dma-names = "tx", "rx";
..
..
@@ -1290,10 +1291,6 @@
1290
1291
 
1291
1292
 		pcfg_pull_default: pcfg_pull_default {
1292
1293
 			bias-pull-pin-default;
1293
-		};
1294
-
1295
-		pcfg_pull_up: pcfg-pull-up {
1296
-			bias-pull-up;
1297
1294
 		};
1298
1295
 
1299
1296
 		pcfg_output_high: pcfg-output-high {
..
..
@@ -1420,8 +1417,8 @@
1420
1417
 
1421
1418
 		uart0 {
1422
1419
 			uart0_xfer: uart0-xfer {
1423
-				rockchip,pins = <2 RK_PD2 2 &pcfg_pull_up>,
1424
-						<2 RK_PD3 2 &pcfg_pull_up>;
1420
+				rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
1421
+						<2 RK_PD3 2 &pcfg_pull_none>;
1425
1422
 			};
1426
1423
 
1427
1424
 			uart0_cts: uart0-cts {
..
..
@@ -1435,8 +1432,8 @@
1435
1432
 
1436
1433
 		uart1 {
1437
1434
 			uart1_xfer: uart1-xfer {
1438
-				rockchip,pins = <1 RK_PB1 2 &pcfg_pull_up>,
1439
-						<1 RK_PB2 2 &pcfg_pull_up>;
1435
+				rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
1436
+						<1 RK_PB2 2 &pcfg_pull_default>;
1440
1437
 			};
1441
1438
 
1442
1439
 			uart1_cts: uart1-cts {
..
..
@@ -1450,8 +1447,8 @@
1450
1447
 
1451
1448
 		uart2 {
1452
1449
 			uart2_xfer: uart2-xfer {
1453
-				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1454
-						<1 RK_PC3 2 &pcfg_pull_up>;
1450
+				rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
1451
+						<1 RK_PC3 2 &pcfg_pull_none>;
1455
1452
 			};
1456
1453
 
1457
1454
 			uart2_cts: uart2-cts {
..
..
@@ -1466,6 +1463,10 @@
1466
1463
 		sdmmc {
1467
1464
 			sdmmc_clk: sdmmc-clk {
1468
1465
 				rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
1466
+			};
1467
+
1468
+			sdmmc_det: sdmmc-det {
1469
+				rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>;
1469
1470
 			};
1470
1471
 
1471
1472
 			sdmmc_cmd: sdmmc-cmd {
..
..
@@ -1607,60 +1608,60 @@
1607
1608
 			};
1608
1609
 		};
1609
1610
 
1610
-		spi {
1611
-			spi0_clk: spi0-clk {
1611
+		spi0 {
1612
+			spi0m0_clk: spi0m0-clk {
1612
1613
 				rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
1613
1614
 			};
1614
1615
 
1615
-			spi0_cs0: spi0-cs0 {
1616
+			spi0m0_cs0: spi0m0-cs0 {
1616
1617
 				rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
1617
1618
 			};
1618
1619
 
1619
-			spi0_tx: spi0-tx {
1620
+			spi0m0_tx: spi0m0-tx {
1620
1621
 				rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
1621
1622
 			};
1622
1623
 
1623
-			spi0_rx: spi0-rx {
1624
+			spi0m0_rx: spi0m0-rx {
1624
1625
 				rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
1625
1626
 			};
1626
1627
 
1627
-			spi0_cs1: spi0-cs1 {
1628
+			spi0m0_cs1: spi0m0-cs1 {
1628
1629
 				rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
1629
1630
 			};
1630
1631
 
1631
-			spi1_clk: spi1-clk {
1632
+			spi0m1_clk: spi0m1-clk {
1632
1633
 				rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
1633
1634
 			};
1634
1635
 
1635
-			spi1_cs0: spi1-cs0 {
1636
+			spi0m1_cs0: spi0m1-cs0 {
1636
1637
 				rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
1637
1638
 			};
1638
1639
 
1639
-			spi1_tx: spi1-tx {
1640
+			spi0m1_tx: spi0m1-tx {
1640
1641
 				rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
1641
1642
 			};
1642
1643
 
1643
-			spi1_rx: spi1-rx {
1644
+			spi0m1_rx: spi0m1-rx {
1644
1645
 				rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
1645
1646
 			};
1646
1647
 
1647
-			spi1_cs1: spi1-cs1 {
1648
+			spi0m1_cs1: spi0m1-cs1 {
1648
1649
 				rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
1649
1650
 			};
1650
1651
 
1651
-			spi2_clk: spi2-clk {
1652
+			spi0m2_clk: spi0m2-clk {
1652
1653
 				rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
1653
1654
 			};
1654
1655
 
1655
-			spi2_cs0: spi2-cs0 {
1656
+			spi0m2_cs0: spi0m2-cs0 {
1656
1657
 				rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
1657
1658
 			};
1658
1659
 
1659
-			spi2_tx: spi2-tx {
1660
+			spi0m2_tx: spi0m2-tx {
1660
1661
 				rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
1661
1662
 			};
1662
1663
 
1663
-			spi2_rx: spi2-rx {
1664
+			spi0m2_rx: spi0m2-rx {
1664
1665
 				rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
1665
1666
 			};
1666
1667
 		};