~hc/RK356X_SDK_RELEASE.git

..	..	@@ -18,6 +18,9 @@
18	18
19	19	aliases {
20	20	ethernet0 = &emac;
	21	+ gpio0 = &gpio0;
	22	+ gpio1 = &gpio1;
	23	+ gpio2 = &gpio2;
21	24	i2c0 = &i2c0;
22	25	i2c1 = &i2c1;
23	26	i2c2 = &i2c2;
..	..	@@ -85,7 +88,7 @@
85	88	};
86	89	};
87	90
88		- amba {
	91	+ amba: bus {
89	92	compatible = "simple-bus";
90	93	#address-cells = <1>;
91	94	#size-cells = <1>;
..	..	@@ -138,7 +141,7 @@
138	141	#clock-cells = <0>;
139	142	};
140	143
141		- bus_intmem@10080000 {
	144	+ bus_intmem: sram@10080000 {
142	145	compatible = "mmio-sram";
143	146	reg = <0x10080000 0x2000>;
144	147	#address-cells = <1>;
..	..	@@ -152,24 +155,40 @@
152	155	};
153	156
154	157	gpu: gpu@10090000 {
155		- compatible = "rockchip,rk3036-mali", "arm,mali-400";
	158	+ compatible = "arm,mali400";
156	159	reg = <0x10090000 0x10000>;
	160	+ upthreshold = <40>;
	161	+ downdifferential = <10>;
	162	+
157	163	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
158		- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
159		- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
160		- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
161		- interrupt-names = "gp",
162		- "gpmmu",
163		- "pp0",
164		- "ppmmu0";
	164	+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	165	+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	166	+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
	167	+
	168	+ interrupt-names = "Mali_GP_IRQ",
	169	+ "Mali_GP_MMU_IRQ",
	170	+ "Mali_PP0_IRQ",
	171	+ "Mali_PP0_MMU_IRQ";
	172	+
	173	+ clocks = <&cru SCLK_GPU>;
	174	+ clock-names = "clk_mali";
165	175	assigned-clocks = <&cru SCLK_GPU>;
166	176	assigned-clock-rates = <400000000>;
167	177	assigned-clock-parents = <&cru PLL_DPLL>;
	178	+ power-domains = <&power RK3036_PD_GPU>;
168	179	operating-points-v2 = <&gpu_opp_table>;
169		- clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
170		- clock-names = "bus", "core";
171		- resets = <&cru SRST_GPU>;
	180	+
172	181	status = "disabled";
	182	+
	183	+ gpu_power_model: power_model {
	184	+ compatible = "arm,mali-simple-power-model";
	185	+ voltage = <900>;
	186	+ frequency = <500>;
	187	+ static-power = <300>;
	188	+ dynamic-power = <396>;
	189	+ ts = <32000 4700 (-80) 2>;
	190	+ thermal-zone = "soc-thermal";
	191	+ };
173	192	};
174	193
175	194	gpu_opp_table: opp-table1 {
..	..	@@ -185,34 +204,36 @@
185	204	};
186	205	};
187	206
188		- vpu: video-codec@10108000 {
189		- compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
190		- reg = <0x10108000 0x800>;
191		- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
192		- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
193		- interrupt-names = "vepu", "vdpu";
194		- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
195		- clock-names = "aclk", "hclk";
196		- iommus = <&vpu_mmu>;
197		- /*
198		- * 3036's vpu could not run higher than 300M
199		- */
200		- assigned-clocks = <&cru ACLK_VCODEC>;
201		- assigned-clock-rates = <297000000>;
202		- assigned-clock-parents = <&cru PLL_GPLL>;
203		- power-domains = <&power RK3036_PD_VPU>;
	207	+ mpp_srv: mpp-srv {
	208	+ compatible = "rockchip,mpp-service";
	209	+ rockchip,taskqueue-count = <1>;
	210	+ rockchip,resetgroup-count = <1>;
	211	+ rockchip,grf = <&grf>;
	212	+ rockchip,grf-offset = <0x0144>;
	213	+ rockchip,grf-values = <0x0008000a>, <0x00080002>;
	214	+ rockchip,grf-names = "grf_rkvdec", "grf_vdpu1";
204	215	status = "disabled";
205	216	};
206	217
207		- vpu_service: vpu-service@10108400 {
208		- compatible = "rockchip,sub";
	218	+ vdpu: vdpu@10108400 {
	219	+ compatible = "rockchip,vpu-decoder-rk3036";
209	220	reg = <0x10108400 0x400>;
210		- dev_mode = <0>;
211	221	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
212	222	interrupt-names = "irq_dec";
	223	+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	224	+ clock-names = "aclk_vcodec", "hclk_vcodec";
	225	+ rockchip,normal-rates = <297000000>, <0>;
	226	+ assigned-clocks = <&cru ACLK_VCODEC>;
	227	+ assigned-clock-rates = <297000000>;
	228	+ assigned-clock-parents = <&cru PLL_GPLL>;
	229	+ resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
	230	+ reset-names = "shared_video_a", "shared_video_h";
213	231	iommus = <&vpu_mmu>;
214		- allocator = <1>;
215	232	power-domains = <&power RK3036_PD_VPU>;
	233	+ rockchip,srv = <&mpp_srv>;
	234	+ rockchip,taskqueue-node = <0>;
	235	+ rockchip,resetgroup-node = <0>;
	236	+ status = "disabled";
216	237	};
217	238
218	239	vpu_mmu: iommu@10108800 {
..	..	@@ -220,20 +241,32 @@
220	241	reg = <0x10108800 0x100>;
221	242	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
222	243	interrupt-names = "vpu_mmu";
	244	+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	245	+ clock-names = "aclk", "iface";
223	246	#iommu-cells = <0>;
224	247	power-domains = <&power RK3036_PD_VPU>;
225	248	status = "disabled";
226	249	};
227	250
228		- hevc_service: hevc-service@1010c000 {
229		- compatible = "rockchip,sub";
	251	+ hevc: hevc_service@1010c000 {
	252	+ compatible = "rockchip,hevc-decoder-rk3036";
230	253	reg = <0x1010c000 0x400>;
231		- dev_mode = <1>;
232	254	interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
233	255	interrupt-names = "irq_dec";
234		- allocator = <1>;
	256	+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>, <&cru ACLK_HEVC>;
	257	+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
	258	+ rockchip,normal-rates = <297000000>, <0>, <200000000>;
	259	+ assigned-clocks = <&cru ACLK_VCODEC>;
	260	+ assigned-clock-rates = <297000000>;
	261	+ assigned-clock-parents = <&cru PLL_GPLL>;
	262	+ resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>, <&cru SRST_HEVC>;
	263	+ reset-names = "shared_video_a", "shared_video_h", "video_core";
235	264	iommus = <&hevc_mmu>;
	265	+ rockchip,srv = <&mpp_srv>;
	266	+ rockchip,taskqueue-node = <0>;
	267	+ rockchip,resetgroup-node = <0>;
236	268	power-domains = <&power RK3036_PD_VPU>;
	269	+ status = "disabled";
237	270	};
238	271
239	272	hevc_mmu: iommu@1010c440 {
..	..	@@ -241,28 +274,9 @@
241	274	reg = <0x1010c440 0x40>, <0x1010c480 0x40>;
242	275	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
243	276	interrupt-names = "hevc_mmu";
	277	+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
	278	+ clock-names = "aclk", "iface";
244	279	#iommu-cells = <0>;
245		- power-domains = <&power RK3036_PD_VPU>;
246		- status = "disabled";
247		- };
248		-
249		- vpu_combo: vpu-combo {
250		- compatible = "rockchip,vpu_combo";
251		- rockchip,grf = <&grf>;
252		- subcnt = <2>;
253		- rockchip,sub = <&hevc_service>, <&vpu_service>;
254		- mode_bit = <3>;
255		- mode_ctrl = <0x144>;
256		- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>,
257		- <&cru ACLK_HEVC>;
258		- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
259		- /* RK3036's vpu could not run higher than 300M */
260		- assigned-clocks = <&cru ACLK_VCODEC>;
261		- assigned-clock-rates = <297000000>;
262		- assigned-clock-parents = <&cru PLL_GPLL>;
263		- resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>,
264		- <&cru SRST_HEVC>;
265		- reset-names = "video_a", "video_h", "video";
266	280	power-domains = <&power RK3036_PD_VPU>;
267	281	status = "disabled";
268	282	};
..	..	@@ -284,6 +298,37 @@
284	298	vop_out_hdmi: endpoint@0 {
285	299	reg = <0>;
286	300	remote-endpoint = <&hdmi_in_vop>;
	301	+ };
	302	+ vop_out_tve: endpoint@1 {
	303	+ reg = <1>;
	304	+ remote-endpoint = <&tve_in_vop>;
	305	+ };
	306	+ };
	307	+ };
	308	+
	309	+ tve: tve@10118200 {
	310	+ compatible = "rockchip,rk3036-tve";
	311	+ reg = <0x10118200 0x100>;
	312	+ clocks = <&cru ACLK_VIO>;
	313	+ clock-names = "aclk";
	314	+ rockchip,saturation = <0x00386346>;
	315	+ rockchip,brightcontrast = <0x00008b00>;
	316	+ rockchip,adjtiming = <0xa6c00880>;
	317	+ rockchip,lumafilter0 = <0x02ff0000>;
	318	+ rockchip,lumafilter1 = <0xf40202fd>;
	319	+ rockchip,lumafilter2 = <0xf332d919>;
	320	+ rockchip,daclevel = <0x3e>;
	321	+ rockchip,grf = <&grf>;
	322	+ status = "disabled";
	323	+
	324	+ ports {
	325	+ tve_in: port {
	326	+ #address-cells = <1>;
	327	+ #size-cells = <0>;
	328	+ tve_in_vop: endpoint@0 {
	329	+ reg = <0>;
	330	+ remote-endpoint = <&vop_out_tve>;
	331	+ };
287	332	};
288	333	};
289	334	};
..	..	@@ -363,6 +408,20 @@
363	408	status = "disabled";
364	409	};
365	410
	411	+ spdif_tx: spdif-tx@10204000 {
	412	+ compatible = "rockchip,rk3066-spdif";
	413	+ reg = <0x10204000 0x1000>;
	414	+ clocks = <&cru SCLK_SPDIF>, <&cru SCLK_SPDIF>;
	415	+ clock-names = "mclk", "hclk";
	416	+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
	417	+ dmas = <&pdma 13>;
	418	+ dma-names = "tx";
	419	+ pinctrl-names = "default";
	420	+ pinctrl-0 = <&spdif_out>;
	421	+ #sound-dai-cells = <0>;
	422	+ status = "disabled";
	423	+ };
	424	+
366	425	sfc: sfc@10208000 {
367	426	compatible = "rockchip,sfc";
368	427	reg = <0x10208000 0x200>;
..	..	@@ -383,10 +442,12 @@
383	442	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
384	443	resets = <&cru SRST_MMC0>;
385	444	reset-names = "reset";
	445	+ no-mmc;
	446	+ no-sdio;
386	447	status = "disabled";
387	448	};
388	449
389		- sdio: dwmmc@10218000 {
	450	+ sdio: mmc@10218000 {
390	451	compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
391	452	reg = <0x10218000 0x4000>;
392	453	max-frequency = <37500000>;
..	..	@@ -397,10 +458,12 @@
397	458	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
398	459	resets = <&cru SRST_SDIO>;
399	460	reset-names = "reset";
	461	+ no-mmc;
	462	+ no-sd;
400	463	status = "disabled";
401	464	};
402	465
403		- emmc: dwmmc@1021c000 {
	466	+ emmc: mmc@1021c000 {
404	467	compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
405	468	reg = <0x1021c000 0x4000>;
406	469	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
..	..	@@ -411,13 +474,14 @@
411	474	clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
412	475	<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
413	476	clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
414		- default-sample-phase = <158>;
	477	+ rockchip,default-sample-phase = <158>;
415	478	disable-wp;
416	479	dmas = <&pdma 12>;
417	480	dma-names = "rx-tx";
418	481	fifo-depth = <0x100>;
419	482	non-removable;
420		- supports-emmc;
	483	+ no-sdio;
	484	+ no-sd;
421	485	pinctrl-names = "default";
422	486	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
423	487	resets = <&cru SRST_EMMC>;
..	..	@@ -429,8 +493,6 @@
429	493	compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
430	494	reg = <0x10220000 0x4000>;
431	495	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
432		- #address-cells = <1>;
433		- #size-cells = <0>;
434	496	clock-names = "i2s_clk", "i2s_hclk";
435	497	clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
436	498	assigned-clocks = <&cru SCLK_I2S_PRE>;
..	..	@@ -440,7 +502,13 @@
440	502	resets = <&cru SRST_I2S>;
441	503	reset-names = "reset-m";
442	504	pinctrl-names = "default";
443		- pinctrl-0 = <&i2s_bus>;
	505	+ pinctrl-0 = <&i2s_mclk
	506	+ &i2s_sclk
	507	+ &i2s_lrclkrx
	508	+ &i2s_lrclktx
	509	+ &i2s_sdo
	510	+ &i2s_sdi>;
	511	+ #sound-dai-cells = <0>;
444	512	status = "disabled";
445	513	};
446	514
..	..	@@ -457,6 +525,8 @@
457	525	grf: syscon@20008000 {
458	526	compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
459	527	reg = <0x20008000 0x1000>;
	528	+ #address-cells = <1>;
	529	+ #size-cells = <1>;
460	530
461	531	reboot-mode {
462	532	compatible = "syscon-reboot-mode";
..	..	@@ -481,12 +551,42 @@
481	551	<&cru ACLK_HEVC>;
482	552	pm_qos = <&qos_vpu>;
483	553	};
	554	+ pd_gpu@RK3036_PD_GPU {
	555	+ reg = <RK3036_PD_GPU>;
	556	+ clocks = <&cru SCLK_GPU>;
	557	+ };
	558	+ };
484	559
	560	+ usb2phy: usb2-phy@17c {
	561	+ compatible = "rockchip,rk3036-usb2phy";
	562	+ reg = <0x017c 0x0c>;
	563	+ clocks = <&cru SCLK_OTGPHY0>;
	564	+ clock-names = "phyclk";
	565	+ #clock-cells = <0>;
	566	+ clock-output-names = "usb480m_phy";
	567	+ status = "disabled";
	568	+
	569	+ u2phy_otg: otg-port {
	570	+ #phy-cells = <0>;
	571	+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	572	+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
	573	+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
	574	+ interrupt-names = "otg-bvalid", "otg-id",
	575	+ "linestate";
	576	+ status = "disabled";
	577	+ };
	578	+
	579	+ u2phy_host: host-port {
	580	+ #phy-cells = <0>;
	581	+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
	582	+ interrupt-names = "linestate";
	583	+ status = "disabled";
	584	+ };
485	585	};
486	586	};
487	587
488	588	acodec: acodec-ana@20030000 {
489		- compatible = "rk3036-codec";
	589	+ compatible = "rockchip,rk3036-codec";
490	590	reg = <0x20030000 0x4000>;
491	591	rockchip,grf = <&grf>;
492	592	clock-names = "acodec_pclk";
..	..	@@ -518,25 +618,6 @@
518	618	};
519	619	};
520	620
521		- hdmi_sound: hdmi-sound {
522		- compatible = "simple-audio-card";
523		- simple-audio-card,name = "rockchip,hdmi";
524		- simple-audio-card,widgets = "Headphone", "Out Jack",
525		- "Line", "In Jack";
526		- status = "disabled";
527		-
528		- simple-audio-card,dai-link {
529		- format = "i2s";
530		- mclk-fs = <256>;
531		- cpu {
532		- sound-dai = <&i2s>;
533		- };
534		- codec {
535		- sound-dai = <&hdmi>;
536		- };
537		- };
538		- };
539		-
540	621	timer: timer@20044000 {
541	622	compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
542	623	reg = <0x20044000 0x20>;
..	..	@@ -553,7 +634,7 @@
553	634	};
554	635
555	636	pwm0: pwm@20050000 {
556		- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	637	+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
557	638	reg = <0x20050000 0x10>;
558	639	#pwm-cells = <3>;
559	640	clocks = <&cru PCLK_PWM>;
..	..	@@ -564,7 +645,7 @@
564	645	};
565	646
566	647	pwm1: pwm@20050010 {
567		- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	648	+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
568	649	reg = <0x20050010 0x10>;
569	650	#pwm-cells = <3>;
570	651	clocks = <&cru PCLK_PWM>;
..	..	@@ -575,7 +656,7 @@
575	656	};
576	657
577	658	pwm2: pwm@20050020 {
578		- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	659	+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
579	660	reg = <0x20050020 0x10>;
580	661	#pwm-cells = <3>;
581	662	clocks = <&cru PCLK_PWM>;
..	..	@@ -586,9 +667,10 @@
586	667	};
587	668
588	669	pwm3: pwm@20050030 {
589		- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
	670	+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
590	671	reg = <0x20050030 0x10>;
591		- #pwm-cells = <2>;
	672	+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
	673	+ #pwm-cells = <3>;
592	674	clocks = <&cru PCLK_PWM>;
593	675	clock-names = "pwm";
594	676	pinctrl-names = "active";
..	..	@@ -681,7 +763,7 @@
681	763	compatible = "rockchip,rockchip-spi";
682	764	reg = <0x20074000 0x1000>;
683	765	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
684		- clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
	766	+ clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
685	767	clock-names = "apb-pclk","spi_pclk";
686	768	dmas = <&pdma 8>, <&pdma 9>;
687	769	dma-names = "tx", "rx";
..	..	@@ -703,6 +785,7 @@
703	785	compatible = "rockchip,gpio-bank";
704	786	reg = <0x2007c000 0x100>;
705	787	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
	788	+ clock-names = "bus";
706	789	clocks = <&cru PCLK_GPIO0>;
707	790
708	791	gpio-controller;
..	..	@@ -716,6 +799,7 @@
716	799	compatible = "rockchip,gpio-bank";
717	800	reg = <0x20080000 0x100>;
718	801	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
	802	+ clock-names = "bus";
719	803	clocks = <&cru PCLK_GPIO1>;
720	804
721	805	gpio-controller;
..	..	@@ -729,6 +813,7 @@
729	813	compatible = "rockchip,gpio-bank";
730	814	reg = <0x20084000 0x100>;
731	815	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
	816	+ clock-names = "bus";
732	817	clocks = <&cru PCLK_GPIO2>;
733	818
734	819	gpio-controller;
..	..	@@ -742,35 +827,31 @@
742	827	bias-pull-pin-default;
743	828	};
744	829
745		- pcfg_pull_up: pcfg-pull-up {
746		- bias-pull-up;
747		- };
748		-
749	830	pcfg_pull_none: pcfg-pull-none {
750	831	bias-disable;
751	832	};
752	833
753	834	pwm0 {
754	835	pwm0_pin: pwm0-pin {
755		- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
	836	+ rockchip,pins = <0 RK_PA0 2 &pcfg_pull_default>;
756	837	};
757	838	};
758	839
759	840	pwm1 {
760	841	pwm1_pin: pwm1-pin {
761		- rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
	842	+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
762	843	};
763	844	};
764	845
765	846	pwm2 {
766	847	pwm2_pin: pwm2-pin {
767		- rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
	848	+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
768	849	};
769	850	};
770	851
771	852	pwm3 {
772	853	pwm3_pin: pwm3-pin {
773		- rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
	854	+ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_default>;
774	855	};
775	856	};
776	857
..	..	@@ -845,6 +926,12 @@
845	926	};
846	927	};
847	928
	929	+ spdif_tx {
	930	+ spdif_out: spdif-out {
	931	+ rockchip,pins = <0 RK_PD4 1 &pcfg_pull_default>;
	932	+ };
	933	+ };
	934	+
848	935	emac {
849	936	emac_xfer: emac-xfer {
850	937	rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
..	..	@@ -885,20 +972,30 @@
885	972	};
886	973
887	974	i2s {
888		- i2s_bus: i2s-bus {
889		- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
890		- <1 RK_PA1 1 &pcfg_pull_default>,
891		- <1 RK_PA2 1 &pcfg_pull_default>,
892		- <1 RK_PA3 1 &pcfg_pull_default>,
893		- <1 RK_PA4 1 &pcfg_pull_default>,
894		- <1 RK_PA5 1 &pcfg_pull_default>;
	975	+ i2s_mclk: i2s-mclk {
	976	+ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>;
	977	+ };
	978	+ i2s_sclk: i2s-sclk {
	979	+ rockchip,pins = <1 RK_PA1 1 &pcfg_pull_default>;
	980	+ };
	981	+ i2s_lrclkrx: i2s-lrclkrx {
	982	+ rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
	983	+ };
	984	+ i2s_lrclktx: i2s-lrclktx {
	985	+ rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
	986	+ };
	987	+ i2s_sdo: i2s-sdo {
	988	+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>;
	989	+ };
	990	+ i2s_sdi: i2s-sdi {
	991	+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_default>;
895	992	};
896	993	};
897	994
898	995	hdmi {
899	996	hdmi_ctl: hdmi-ctl {
900		- rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
901		- <1 RK_PB1 1 &pcfg_pull_none>,
	997	+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
	998	+ <1 RK_PB1 1 &pcfg_pull_none>,
902	999	<1 RK_PB2 1 &pcfg_pull_none>,
903	1000	<1 RK_PB3 1 &pcfg_pull_none>;
904	1001	};
..	..	@@ -906,8 +1003,8 @@
906	1003
907	1004	uart0 {
908	1005	uart0_xfer: uart0-xfer {
909		- rockchip,pins = <0 RK_PC0 1 &pcfg_pull_up>,
910		- <0 RK_PC1 1 &pcfg_pull_up>;
	1006	+ rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
	1007	+ <0 RK_PC1 1 &pcfg_pull_default>;
911	1008	};
912	1009
913	1010	uart0_cts: uart0-cts {
..	..	@@ -921,16 +1018,16 @@
921	1018
922	1019	uart1 {
923	1020	uart1_xfer: uart1-xfer {
924		- rockchip,pins = <2 RK_PC6 1 &pcfg_pull_up>,
925		- <2 RK_PC7 1 &pcfg_pull_up>;
	1021	+ rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
	1022	+ <2 RK_PC7 1 &pcfg_pull_default>;
926	1023	};
927	1024	/* no rts / cts for uart1 */
928	1025	};
929	1026
930	1027	uart2 {
931	1028	uart2_xfer: uart2-xfer {
932		- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
933		- <1 RK_PC3 2 &pcfg_pull_up>;
	1029	+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
	1030	+ <1 RK_PC3 2 &pcfg_pull_default>;
934	1031	};
935	1032	/* no rts / cts for uart2 */
936	1033	};