add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/r8a7779.dtsi
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@@ -1,6 +1,6 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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- * Device Tree Source for Renesas r8a7779
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+ * Device Tree Source for the R-Car H1 (R8A77790) SoC
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  *
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  * Copyright (C) 2013 Renesas Solutions Corp.
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  * Copyright (C) 2013 Simon Horman
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@@ -172,10 +172,10 @@
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 			<0xfe780044 4>,
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 			<0xfe780064 4>,
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 			<0xfe780000 4>;
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-		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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 		sense-bitfield-width = <2>;
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 	};
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@@ -295,7 +295,33 @@
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 		status = "disabled";
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 	};
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-	pfc: pin-controller@fffc0000 {
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+	hscif0: serial@ffe48000 {
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+		compatible = "renesas,hscif-r8a7779",
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+			     "renesas,rcar-gen1-hscif", "renesas,hscif";
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+		reg = <0xffe48000 96>;
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+		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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+		clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
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+			 <&cpg_clocks R8A7779_CLK_S>,
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+			 <&scif_clk>;
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+		clock-names = "fck", "brg_int", "scif_clk";
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+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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+		status = "disabled";
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+	};
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+
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+	hscif1: serial@ffe49000 {
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+		compatible = "renesas,hscif-r8a7779",
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+			     "renesas,rcar-gen1-hscif", "renesas,hscif";
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+		reg = <0xffe49000 96>;
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+		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
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+		clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
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+			 <&cpg_clocks R8A7779_CLK_S>,
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+			 <&scif_clk>;
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+		clock-names = "fck", "brg_int", "scif_clk";
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+		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
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+		status = "disabled";
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+	};
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+
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+	pfc: pinctrl@fffc0000 {
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 		compatible = "renesas,pfc-r8a7779";
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 		reg = <0xfffc0000 0x23c>;
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 	};
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@@ -351,7 +377,7 @@
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 	};
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 	sata: sata@fc600000 {
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-		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
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+		compatible = "renesas,sata-r8a7779";
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 		reg = <0xfc600000 0x200000>;
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 		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
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@@ -359,7 +385,7 @@
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 		status = "disabled";
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 	};
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-	sdhi0: sd@ffe4c000 {
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+	sdhi0: mmc@ffe4c000 {
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 		compatible = "renesas,sdhi-r8a7779",
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 			     "renesas,rcar-gen1-sdhi";
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 		reg = <0xffe4c000 0x100>;
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@@ -369,7 +395,7 @@
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 		status = "disabled";
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 	};
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-	sdhi1: sd@ffe4d000 {
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+	sdhi1: mmc@ffe4d000 {
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 		compatible = "renesas,sdhi-r8a7779",
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 			     "renesas,rcar-gen1-sdhi";
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 		reg = <0xffe4d000 0x100>;
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@@ -379,7 +405,7 @@
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 		status = "disabled";
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 	};
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-	sdhi2: sd@ffe4e000 {
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+	sdhi2: mmc@ffe4e000 {
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 		compatible = "renesas,sdhi-r8a7779",
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 			     "renesas,rcar-gen1-sdhi";
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 		reg = <0xffe4e000 0x100>;
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@@ -389,7 +415,7 @@
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 		status = "disabled";
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 	};
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-	sdhi3: sd@ffe4f000 {
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+	sdhi3: mmc@ffe4f000 {
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 		compatible = "renesas,sdhi-r8a7779",
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 			     "renesas,rcar-gen1-sdhi";
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 		reg = <0xffe4f000 0x100>;