add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/r8a7740.dtsi
..
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@@ -1,6 +1,6 @@
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 // SPDX-License-Identifier: GPL-2.0
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 /*
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- * Device Tree Source for the r8a7740 SoC
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+ * Device Tree Source for the R-Mobile A1 (R8A77400) SoC
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  *
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  * Copyright (C) 2012 Renesas Solutions Corp.
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  */
..
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@@ -83,7 +83,7 @@
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 	};
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 	cmt1: timer@e6138000 {
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-		compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48";
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+		compatible = "renesas,r8a7740-cmt1";
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 		reg = <0xe6138000 0x170>;
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 		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp3_clks R8A7740_CLK_CMT1>;
..
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@@ -102,14 +102,14 @@
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 			<0xe6900020 1>,
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 			<0xe6900040 1>,
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 			<0xe6900060 1>;
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-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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 		power-domains = <&pd_a4s>;
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 	};
..
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@@ -124,14 +124,14 @@
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 			<0xe6900024 1>,
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 			<0xe6900044 1>,
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 			<0xe6900064 1>;
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-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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 		power-domains = <&pd_a4s>;
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 	};
..
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@@ -146,14 +146,14 @@
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 			<0xe6900028 1>,
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 			<0xe6900048 1>,
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 			<0xe6900068 1>;
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-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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 		power-domains = <&pd_a4s>;
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 	};
..
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@@ -168,14 +168,14 @@
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 			<0xe690002c 1>,
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 			<0xe690004c 1>,
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 			<0xe690006c 1>;
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-		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp2_clks R8A7740_CLK_INTCA>;
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 		power-domains = <&pd_a4s>;
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 	};
..
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@@ -198,10 +198,10 @@
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 		#size-cells = <0>;
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 		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
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 		reg = <0xfff20000 0x425>;
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-		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp1_clks R8A7740_CLK_IIC0>;
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 		power-domains = <&pd_a4r>;
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 		status = "disabled";
..
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@@ -212,10 +212,10 @@
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 		#size-cells = <0>;
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 		compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
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 		reg = <0xe6c20000 0x425>;
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-		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp3_clks R8A7740_CLK_IIC1>;
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 		power-domains = <&pd_a3sp>;
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 		status = "disabled";
..
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@@ -311,7 +311,7 @@
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 		status = "disabled";
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 	};
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-	pfc: pin-controller@e6050000 {
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+	pfc: pinctrl@e6050000 {
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 		compatible = "renesas,pfc-r8a7740";
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 		reg = <0xe6050000 0x8000>,
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 		      <0xe605800c 0x20>;
..
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@@ -342,19 +342,19 @@
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 	mmcif0: mmc@e6bd0000 {
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 		compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
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 		reg = <0xe6bd0000 0x100>;
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-		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp3_clks R8A7740_CLK_MMC>;
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 		power-domains = <&pd_a3sp>;
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 		status = "disabled";
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 	};
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-	sdhi0: sd@e6850000 {
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+	sdhi0: mmc@e6850000 {
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 		compatible = "renesas,sdhi-r8a7740";
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 		reg = <0xe6850000 0x100>;
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-		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp3_clks R8A7740_CLK_SDHI0>;
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 		power-domains = <&pd_a3sp>;
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 		cap-sd-highspeed;
..
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@@ -362,12 +362,12 @@
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 		status = "disabled";
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 	};
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364
 
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-	sdhi1: sd@e6860000 {
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+	sdhi1: mmc@e6860000 {
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 		compatible = "renesas,sdhi-r8a7740";
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 		reg = <0xe6860000 0x100>;
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-		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp3_clks R8A7740_CLK_SDHI1>;
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 		power-domains = <&pd_a3sp>;
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 		cap-sd-highspeed;
..
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@@ -375,12 +375,12 @@
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 		status = "disabled";
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 	};
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-	sdhi2: sd@e6870000 {
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+	sdhi2: mmc@e6870000 {
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 		compatible = "renesas,sdhi-r8a7740";
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 		reg = <0xe6870000 0x100>;
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-		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH
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-			      GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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+		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+			     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&mstp4_clks R8A7740_CLK_SDHI2>;
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 		power-domains = <&pd_a3sp>;
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 		cap-sd-highspeed;