add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/pxa168.dtsi
..
..
@@ -1,16 +1,15 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  *  Copyright (C) 2012 Marvell Technology Group Ltd.
3
4
  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
4
- *
5
- *  This program is free software; you can redistribute it and/or modify
6
- *  it under the terms of the GNU General Public License version 2 as
7
- *  publishhed by the Free Software Foundation.
8
5
  */
9
6
 
10
-#include "skeleton.dtsi"
11
7
 #include <dt-bindings/clock/marvell,pxa168.h>
12
8
 
13
9
 / {
10
+	#address-cells = <1>;
11
+	#size-cells = <1>;
12
+
14
13
 	aliases {
15
14
 		serial0 = &uart1;
16
15
 		serial1 = &uart2;
..
..
@@ -56,27 +55,30 @@
56
55
 				interrupts = <13>;
57
56
 			};
58
57
 
59
-			uart1: uart@d4017000 {
60
-				compatible = "mrvl,mmp-uart";
58
+			uart1: serial@d4017000 {
59
+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
61
60
 				reg = <0xd4017000 0x1000>;
61
+				reg-shift = <2>;
62
62
 				interrupts = <27>;
63
63
 				clocks = <&soc_clocks PXA168_CLK_UART0>;
64
64
 				resets = <&soc_clocks PXA168_CLK_UART0>;
65
65
 				status = "disabled";
66
66
 			};
67
67
 
68
-			uart2: uart@d4018000 {
69
-				compatible = "mrvl,mmp-uart";
68
+			uart2: serial@d4018000 {
69
+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
70
70
 				reg = <0xd4018000 0x1000>;
71
+				reg-shift = <2>;
71
72
 				interrupts = <28>;
72
73
 				clocks = <&soc_clocks PXA168_CLK_UART1>;
73
74
 				resets = <&soc_clocks PXA168_CLK_UART1>;
74
75
 				status = "disabled";
75
76
 			};
76
77
 
77
-			uart3: uart@d4026000 {
78
-				compatible = "mrvl,mmp-uart";
78
+			uart3: serial@d4026000 {
79
+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
79
80
 				reg = <0xd4026000 0x1000>;
81
+				reg-shift = <2>;
80
82
 				interrupts = <29>;
81
83
 				clocks = <&soc_clocks PXA168_CLK_UART2>;
82
84
 				resets = <&soc_clocks PXA168_CLK_UART2>;
..
..
@@ -95,7 +97,7 @@
95
97
 				resets = <&soc_clocks PXA168_CLK_GPIO>;
96
98
 				interrupt-names = "gpio_mux";
97
99
 				interrupt-controller;
98
-				#interrupt-cells = <1>;
100
+				#interrupt-cells = <2>;
99
101
 				ranges;
100
102
 
101
103
 				gcb0: gpio@d4019000 {
..
..
@@ -117,6 +119,8 @@
117
119
 
118
120
 			twsi1: i2c@d4011000 {
119
121
 				compatible = "mrvl,mmp-twsi";
122
+				#address-cells = <1>;
123
+				#size-cells = <0>;
120
124
 				reg = <0xd4011000 0x1000>;
121
125
 				interrupts = <7>;
122
126
 				clocks = <&soc_clocks PXA168_CLK_TWSI0>;
..
..
@@ -127,6 +131,8 @@
127
131
 
128
132
 			twsi2: i2c@d4025000 {
129
133
 				compatible = "mrvl,mmp-twsi";
134
+				#address-cells = <1>;
135
+				#size-cells = <0>;
130
136
 				reg = <0xd4025000 0x1000>;
131
137
 				interrupts = <58>;
132
138
 				clocks = <&soc_clocks PXA168_CLK_TWSI1>;
..
..
@@ -137,7 +143,7 @@
137
143
 			rtc: rtc@d4010000 {
138
144
 				compatible = "mrvl,mmp-rtc";
139
145
 				reg = <0xd4010000 0x1000>;
140
-				interrupts = <5 6>;
146
+				interrupts = <5>, <6>;
141
147
 				interrupt-names = "rtc 1Hz", "rtc alarm";
142
148
 				clocks = <&soc_clocks PXA168_CLK_RTC>;
143
149
 				resets = <&soc_clocks PXA168_CLK_RTC>;