.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | | - * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ |
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| 3 | + * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
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3 | 4 | * |
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4 | | - * This program is free software; you can redistribute it and/or modify |
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5 | | - * it under the terms of the GNU General Public License version 2 as |
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6 | | - * published by the Free Software Foundation. |
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7 | 5 | * Based on "omap4.dtsi" |
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8 | 6 | */ |
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9 | 7 | |
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| 8 | +#include <dt-bindings/bus/ti-sysc.h> |
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10 | 9 | #include <dt-bindings/gpio/gpio.h> |
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11 | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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12 | 11 | #include <dt-bindings/pinctrl/omap.h> |
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.. | .. |
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37 | 36 | serial3 = &uart4; |
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38 | 37 | serial4 = &uart5; |
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39 | 38 | serial5 = &uart6; |
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| 39 | + rproc0 = &dsp; |
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| 40 | + rproc1 = &ipu; |
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40 | 41 | }; |
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41 | 42 | |
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42 | 43 | cpus { |
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.. | .. |
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157 | 158 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
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158 | 159 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
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159 | 160 | |
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160 | | - l4_cfg: l4@4a000000 { |
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161 | | - compatible = "ti,omap5-l4-cfg", "simple-bus"; |
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162 | | - #address-cells = <1>; |
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163 | | - #size-cells = <1>; |
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164 | | - ranges = <0 0x4a000000 0x22a000>; |
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165 | | - |
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166 | | - scm_core: scm@2000 { |
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167 | | - compatible = "ti,omap5-scm-core", "simple-bus"; |
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168 | | - reg = <0x2000 0x1000>; |
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169 | | - #address-cells = <1>; |
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170 | | - #size-cells = <1>; |
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171 | | - ranges = <0 0x2000 0x800>; |
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172 | | - |
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173 | | - scm_conf: scm_conf@0 { |
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174 | | - compatible = "syscon"; |
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175 | | - reg = <0x0 0x800>; |
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176 | | - #address-cells = <1>; |
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177 | | - #size-cells = <1>; |
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178 | | - }; |
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179 | | - }; |
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180 | | - |
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181 | | - scm_padconf_core: scm@2800 { |
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182 | | - compatible = "ti,omap5-scm-padconf-core", |
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183 | | - "simple-bus"; |
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184 | | - #address-cells = <1>; |
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185 | | - #size-cells = <1>; |
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186 | | - ranges = <0 0x2800 0x800>; |
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187 | | - |
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188 | | - omap5_pmx_core: pinmux@40 { |
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189 | | - compatible = "ti,omap5-padconf", |
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190 | | - "pinctrl-single"; |
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191 | | - reg = <0x40 0x01b6>; |
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192 | | - #address-cells = <1>; |
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193 | | - #size-cells = <0>; |
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194 | | - #pinctrl-cells = <1>; |
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195 | | - #interrupt-cells = <1>; |
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196 | | - interrupt-controller; |
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197 | | - pinctrl-single,register-width = <16>; |
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198 | | - pinctrl-single,function-mask = <0x7fff>; |
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199 | | - }; |
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200 | | - |
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201 | | - omap5_padconf_global: omap5_padconf_global@5a0 { |
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202 | | - compatible = "syscon", |
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203 | | - "simple-bus"; |
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204 | | - reg = <0x5a0 0xec>; |
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205 | | - #address-cells = <1>; |
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206 | | - #size-cells = <1>; |
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207 | | - ranges = <0 0x5a0 0xec>; |
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208 | | - |
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209 | | - pbias_regulator: pbias_regulator@60 { |
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210 | | - compatible = "ti,pbias-omap5", "ti,pbias-omap"; |
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211 | | - reg = <0x60 0x4>; |
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212 | | - syscon = <&omap5_padconf_global>; |
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213 | | - pbias_mmc_reg: pbias_mmc_omap5 { |
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214 | | - regulator-name = "pbias_mmc_omap5"; |
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215 | | - regulator-min-microvolt = <1800000>; |
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216 | | - regulator-max-microvolt = <3300000>; |
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217 | | - }; |
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218 | | - }; |
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219 | | - }; |
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220 | | - }; |
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221 | | - |
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222 | | - cm_core_aon: cm_core_aon@4000 { |
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223 | | - compatible = "ti,omap5-cm-core-aon", |
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224 | | - "simple-bus"; |
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225 | | - reg = <0x4000 0x2000>; |
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226 | | - #address-cells = <1>; |
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227 | | - #size-cells = <1>; |
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228 | | - ranges = <0 0x4000 0x2000>; |
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229 | | - |
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230 | | - cm_core_aon_clocks: clocks { |
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231 | | - #address-cells = <1>; |
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232 | | - #size-cells = <0>; |
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233 | | - }; |
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234 | | - |
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235 | | - cm_core_aon_clockdomains: clockdomains { |
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236 | | - }; |
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237 | | - }; |
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238 | | - |
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239 | | - cm_core: cm_core@8000 { |
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240 | | - compatible = "ti,omap5-cm-core", "simple-bus"; |
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241 | | - reg = <0x8000 0x3000>; |
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242 | | - #address-cells = <1>; |
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243 | | - #size-cells = <1>; |
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244 | | - ranges = <0 0x8000 0x3000>; |
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245 | | - |
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246 | | - cm_core_clocks: clocks { |
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247 | | - #address-cells = <1>; |
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248 | | - #size-cells = <0>; |
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249 | | - }; |
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250 | | - |
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251 | | - cm_core_clockdomains: clockdomains { |
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252 | | - }; |
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253 | | - }; |
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| 161 | + l4_wkup: interconnect@4ae00000 { |
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254 | 162 | }; |
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255 | 163 | |
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256 | | - l4_wkup: l4@4ae00000 { |
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257 | | - compatible = "ti,omap5-l4-wkup", "simple-bus"; |
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258 | | - #address-cells = <1>; |
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259 | | - #size-cells = <1>; |
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260 | | - ranges = <0 0x4ae00000 0x2b000>; |
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261 | | - |
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262 | | - counter32k: counter@4000 { |
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263 | | - compatible = "ti,omap-counter32k"; |
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264 | | - reg = <0x4000 0x40>; |
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265 | | - ti,hwmods = "counter_32k"; |
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266 | | - }; |
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267 | | - |
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268 | | - prm: prm@6000 { |
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269 | | - compatible = "ti,omap5-prm", "simple-bus"; |
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270 | | - reg = <0x6000 0x3000>; |
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271 | | - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
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272 | | - #address-cells = <1>; |
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273 | | - #size-cells = <1>; |
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274 | | - ranges = <0 0x6000 0x3000>; |
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275 | | - |
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276 | | - prm_clocks: clocks { |
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277 | | - #address-cells = <1>; |
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278 | | - #size-cells = <0>; |
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279 | | - }; |
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280 | | - |
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281 | | - prm_clockdomains: clockdomains { |
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282 | | - }; |
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283 | | - }; |
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284 | | - |
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285 | | - scrm: scrm@a000 { |
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286 | | - compatible = "ti,omap5-scrm"; |
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287 | | - reg = <0xa000 0x2000>; |
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288 | | - |
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289 | | - scrm_clocks: clocks { |
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290 | | - #address-cells = <1>; |
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291 | | - #size-cells = <0>; |
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292 | | - }; |
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293 | | - |
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294 | | - scrm_clockdomains: clockdomains { |
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295 | | - }; |
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296 | | - }; |
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297 | | - |
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298 | | - omap5_pmx_wkup: pinmux@c840 { |
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299 | | - compatible = "ti,omap5-padconf", |
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300 | | - "pinctrl-single"; |
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301 | | - reg = <0xc840 0x003c>; |
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302 | | - #address-cells = <1>; |
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303 | | - #size-cells = <0>; |
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304 | | - #pinctrl-cells = <1>; |
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305 | | - #interrupt-cells = <1>; |
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306 | | - interrupt-controller; |
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307 | | - pinctrl-single,register-width = <16>; |
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308 | | - pinctrl-single,function-mask = <0x7fff>; |
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309 | | - }; |
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310 | | - |
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311 | | - omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 { |
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312 | | - compatible = "ti,omap5-scm-wkup-pad-conf", |
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313 | | - "simple-bus"; |
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314 | | - reg = <0xcda0 0x60>; |
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315 | | - #address-cells = <1>; |
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316 | | - #size-cells = <1>; |
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317 | | - ranges = <0 0xcda0 0x60>; |
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318 | | - |
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319 | | - scm_wkup_pad_conf: scm_conf@0 { |
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320 | | - compatible = "syscon", "simple-bus"; |
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321 | | - reg = <0x0 0x60>; |
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322 | | - #address-cells = <1>; |
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323 | | - #size-cells = <1>; |
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324 | | - ranges = <0 0x0 0x60>; |
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325 | | - |
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326 | | - scm_wkup_pad_conf_clocks: clocks@0 { |
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327 | | - #address-cells = <1>; |
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328 | | - #size-cells = <0>; |
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329 | | - }; |
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330 | | - }; |
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331 | | - }; |
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| 164 | + l4_cfg: interconnect@4a000000 { |
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332 | 165 | }; |
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333 | 166 | |
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334 | | - ocmcram: ocmcram@40300000 { |
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| 167 | + l4_per: interconnect@48000000 { |
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| 168 | + }; |
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| 169 | + |
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| 170 | + l4_abe: interconnect@40100000 { |
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| 171 | + }; |
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| 172 | + |
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| 173 | + ocmcram: sram@40300000 { |
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335 | 174 | compatible = "mmio-sram"; |
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336 | 175 | reg = <0x40300000 0x20000>; /* 128k */ |
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337 | | - }; |
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338 | | - |
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339 | | - sdma: dma-controller@4a056000 { |
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340 | | - compatible = "ti,omap4430-sdma"; |
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341 | | - reg = <0x4a056000 0x1000>; |
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342 | | - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
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343 | | - <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
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344 | | - <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
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345 | | - <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
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346 | | - #dma-cells = <1>; |
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347 | | - dma-channels = <32>; |
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348 | | - dma-requests = <127>; |
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349 | | - ti,hwmods = "dma_system"; |
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350 | | - }; |
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351 | | - |
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352 | | - gpio1: gpio@4ae10000 { |
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353 | | - compatible = "ti,omap4-gpio"; |
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354 | | - reg = <0x4ae10000 0x200>; |
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355 | | - interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
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356 | | - ti,hwmods = "gpio1"; |
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357 | | - ti,gpio-always-on; |
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358 | | - gpio-controller; |
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359 | | - #gpio-cells = <2>; |
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360 | | - interrupt-controller; |
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361 | | - #interrupt-cells = <2>; |
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362 | | - }; |
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363 | | - |
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364 | | - gpio2: gpio@48055000 { |
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365 | | - compatible = "ti,omap4-gpio"; |
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366 | | - reg = <0x48055000 0x200>; |
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367 | | - interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
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368 | | - ti,hwmods = "gpio2"; |
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369 | | - gpio-controller; |
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370 | | - #gpio-cells = <2>; |
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371 | | - interrupt-controller; |
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372 | | - #interrupt-cells = <2>; |
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373 | | - }; |
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374 | | - |
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375 | | - gpio3: gpio@48057000 { |
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376 | | - compatible = "ti,omap4-gpio"; |
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377 | | - reg = <0x48057000 0x200>; |
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378 | | - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
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379 | | - ti,hwmods = "gpio3"; |
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380 | | - gpio-controller; |
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381 | | - #gpio-cells = <2>; |
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382 | | - interrupt-controller; |
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383 | | - #interrupt-cells = <2>; |
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384 | | - }; |
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385 | | - |
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386 | | - gpio4: gpio@48059000 { |
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387 | | - compatible = "ti,omap4-gpio"; |
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388 | | - reg = <0x48059000 0x200>; |
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389 | | - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
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390 | | - ti,hwmods = "gpio4"; |
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391 | | - gpio-controller; |
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392 | | - #gpio-cells = <2>; |
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393 | | - interrupt-controller; |
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394 | | - #interrupt-cells = <2>; |
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395 | | - }; |
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396 | | - |
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397 | | - gpio5: gpio@4805b000 { |
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398 | | - compatible = "ti,omap4-gpio"; |
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399 | | - reg = <0x4805b000 0x200>; |
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400 | | - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
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401 | | - ti,hwmods = "gpio5"; |
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402 | | - gpio-controller; |
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403 | | - #gpio-cells = <2>; |
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404 | | - interrupt-controller; |
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405 | | - #interrupt-cells = <2>; |
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406 | | - }; |
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407 | | - |
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408 | | - gpio6: gpio@4805d000 { |
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409 | | - compatible = "ti,omap4-gpio"; |
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410 | | - reg = <0x4805d000 0x200>; |
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411 | | - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
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412 | | - ti,hwmods = "gpio6"; |
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413 | | - gpio-controller; |
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414 | | - #gpio-cells = <2>; |
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415 | | - interrupt-controller; |
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416 | | - #interrupt-cells = <2>; |
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417 | | - }; |
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418 | | - |
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419 | | - gpio7: gpio@48051000 { |
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420 | | - compatible = "ti,omap4-gpio"; |
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421 | | - reg = <0x48051000 0x200>; |
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422 | | - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
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423 | | - ti,hwmods = "gpio7"; |
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424 | | - gpio-controller; |
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425 | | - #gpio-cells = <2>; |
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426 | | - interrupt-controller; |
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427 | | - #interrupt-cells = <2>; |
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428 | | - }; |
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429 | | - |
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430 | | - gpio8: gpio@48053000 { |
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431 | | - compatible = "ti,omap4-gpio"; |
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432 | | - reg = <0x48053000 0x200>; |
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433 | | - interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
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434 | | - ti,hwmods = "gpio8"; |
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435 | | - gpio-controller; |
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436 | | - #gpio-cells = <2>; |
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437 | | - interrupt-controller; |
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438 | | - #interrupt-cells = <2>; |
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439 | 176 | }; |
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440 | 177 | |
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441 | 178 | gpmc: gpmc@50000000 { |
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.. | .. |
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457 | 194 | #gpio-cells = <2>; |
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458 | 195 | }; |
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459 | 196 | |
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460 | | - i2c1: i2c@48070000 { |
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461 | | - compatible = "ti,omap4-i2c"; |
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462 | | - reg = <0x48070000 0x100>; |
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463 | | - interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
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464 | | - #address-cells = <1>; |
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465 | | - #size-cells = <0>; |
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466 | | - ti,hwmods = "i2c1"; |
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467 | | - }; |
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468 | | - |
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469 | | - i2c2: i2c@48072000 { |
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470 | | - compatible = "ti,omap4-i2c"; |
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471 | | - reg = <0x48072000 0x100>; |
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472 | | - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; |
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473 | | - #address-cells = <1>; |
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474 | | - #size-cells = <0>; |
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475 | | - ti,hwmods = "i2c2"; |
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476 | | - }; |
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477 | | - |
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478 | | - i2c3: i2c@48060000 { |
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479 | | - compatible = "ti,omap4-i2c"; |
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480 | | - reg = <0x48060000 0x100>; |
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481 | | - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
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482 | | - #address-cells = <1>; |
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483 | | - #size-cells = <0>; |
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484 | | - ti,hwmods = "i2c3"; |
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485 | | - }; |
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486 | | - |
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487 | | - i2c4: i2c@4807a000 { |
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488 | | - compatible = "ti,omap4-i2c"; |
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489 | | - reg = <0x4807a000 0x100>; |
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490 | | - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
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491 | | - #address-cells = <1>; |
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492 | | - #size-cells = <0>; |
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493 | | - ti,hwmods = "i2c4"; |
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494 | | - }; |
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495 | | - |
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496 | | - i2c5: i2c@4807c000 { |
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497 | | - compatible = "ti,omap4-i2c"; |
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498 | | - reg = <0x4807c000 0x100>; |
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499 | | - interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
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500 | | - #address-cells = <1>; |
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501 | | - #size-cells = <0>; |
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502 | | - ti,hwmods = "i2c5"; |
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503 | | - }; |
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504 | | - |
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505 | | - hwspinlock: spinlock@4a0f6000 { |
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506 | | - compatible = "ti,omap4-hwspinlock"; |
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507 | | - reg = <0x4a0f6000 0x1000>; |
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508 | | - ti,hwmods = "spinlock"; |
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509 | | - #hwlock-cells = <1>; |
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510 | | - }; |
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511 | | - |
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512 | | - mcspi1: spi@48098000 { |
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513 | | - compatible = "ti,omap4-mcspi"; |
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514 | | - reg = <0x48098000 0x200>; |
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515 | | - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
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516 | | - #address-cells = <1>; |
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517 | | - #size-cells = <0>; |
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518 | | - ti,hwmods = "mcspi1"; |
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519 | | - ti,spi-num-cs = <4>; |
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520 | | - dmas = <&sdma 35>, |
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521 | | - <&sdma 36>, |
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522 | | - <&sdma 37>, |
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523 | | - <&sdma 38>, |
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524 | | - <&sdma 39>, |
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525 | | - <&sdma 40>, |
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526 | | - <&sdma 41>, |
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527 | | - <&sdma 42>; |
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528 | | - dma-names = "tx0", "rx0", "tx1", "rx1", |
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529 | | - "tx2", "rx2", "tx3", "rx3"; |
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530 | | - }; |
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531 | | - |
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532 | | - mcspi2: spi@4809a000 { |
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533 | | - compatible = "ti,omap4-mcspi"; |
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534 | | - reg = <0x4809a000 0x200>; |
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535 | | - interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; |
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536 | | - #address-cells = <1>; |
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537 | | - #size-cells = <0>; |
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538 | | - ti,hwmods = "mcspi2"; |
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539 | | - ti,spi-num-cs = <2>; |
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540 | | - dmas = <&sdma 43>, |
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541 | | - <&sdma 44>, |
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542 | | - <&sdma 45>, |
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543 | | - <&sdma 46>; |
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544 | | - dma-names = "tx0", "rx0", "tx1", "rx1"; |
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545 | | - }; |
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546 | | - |
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547 | | - mcspi3: spi@480b8000 { |
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548 | | - compatible = "ti,omap4-mcspi"; |
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549 | | - reg = <0x480b8000 0x200>; |
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550 | | - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
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551 | | - #address-cells = <1>; |
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552 | | - #size-cells = <0>; |
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553 | | - ti,hwmods = "mcspi3"; |
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554 | | - ti,spi-num-cs = <2>; |
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555 | | - dmas = <&sdma 15>, <&sdma 16>; |
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556 | | - dma-names = "tx0", "rx0"; |
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557 | | - }; |
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558 | | - |
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559 | | - mcspi4: spi@480ba000 { |
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560 | | - compatible = "ti,omap4-mcspi"; |
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561 | | - reg = <0x480ba000 0x200>; |
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562 | | - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
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563 | | - #address-cells = <1>; |
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564 | | - #size-cells = <0>; |
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565 | | - ti,hwmods = "mcspi4"; |
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566 | | - ti,spi-num-cs = <1>; |
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567 | | - dmas = <&sdma 70>, <&sdma 71>; |
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568 | | - dma-names = "tx0", "rx0"; |
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569 | | - }; |
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570 | | - |
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571 | | - uart1: serial@4806a000 { |
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572 | | - compatible = "ti,omap4-uart"; |
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573 | | - reg = <0x4806a000 0x100>; |
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574 | | - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
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575 | | - ti,hwmods = "uart1"; |
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576 | | - clock-frequency = <48000000>; |
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577 | | - }; |
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578 | | - |
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579 | | - uart2: serial@4806c000 { |
---|
580 | | - compatible = "ti,omap4-uart"; |
---|
581 | | - reg = <0x4806c000 0x100>; |
---|
582 | | - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
---|
583 | | - ti,hwmods = "uart2"; |
---|
584 | | - clock-frequency = <48000000>; |
---|
585 | | - }; |
---|
586 | | - |
---|
587 | | - uart3: serial@48020000 { |
---|
588 | | - compatible = "ti,omap4-uart"; |
---|
589 | | - reg = <0x48020000 0x100>; |
---|
590 | | - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
---|
591 | | - ti,hwmods = "uart3"; |
---|
592 | | - clock-frequency = <48000000>; |
---|
593 | | - }; |
---|
594 | | - |
---|
595 | | - uart4: serial@4806e000 { |
---|
596 | | - compatible = "ti,omap4-uart"; |
---|
597 | | - reg = <0x4806e000 0x100>; |
---|
598 | | - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
---|
599 | | - ti,hwmods = "uart4"; |
---|
600 | | - clock-frequency = <48000000>; |
---|
601 | | - }; |
---|
602 | | - |
---|
603 | | - uart5: serial@48066000 { |
---|
604 | | - compatible = "ti,omap4-uart"; |
---|
605 | | - reg = <0x48066000 0x100>; |
---|
606 | | - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; |
---|
607 | | - ti,hwmods = "uart5"; |
---|
608 | | - clock-frequency = <48000000>; |
---|
609 | | - }; |
---|
610 | | - |
---|
611 | | - uart6: serial@48068000 { |
---|
612 | | - compatible = "ti,omap4-uart"; |
---|
613 | | - reg = <0x48068000 0x100>; |
---|
614 | | - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
---|
615 | | - ti,hwmods = "uart6"; |
---|
616 | | - clock-frequency = <48000000>; |
---|
617 | | - }; |
---|
618 | | - |
---|
619 | | - mmc1: mmc@4809c000 { |
---|
620 | | - compatible = "ti,omap4-hsmmc"; |
---|
621 | | - reg = <0x4809c000 0x400>; |
---|
622 | | - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
---|
623 | | - ti,hwmods = "mmc1"; |
---|
624 | | - ti,dual-volt; |
---|
625 | | - ti,needs-special-reset; |
---|
626 | | - dmas = <&sdma 61>, <&sdma 62>; |
---|
627 | | - dma-names = "tx", "rx"; |
---|
628 | | - pbias-supply = <&pbias_mmc_reg>; |
---|
629 | | - }; |
---|
630 | | - |
---|
631 | | - mmc2: mmc@480b4000 { |
---|
632 | | - compatible = "ti,omap4-hsmmc"; |
---|
633 | | - reg = <0x480b4000 0x400>; |
---|
634 | | - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
---|
635 | | - ti,hwmods = "mmc2"; |
---|
636 | | - ti,needs-special-reset; |
---|
637 | | - dmas = <&sdma 47>, <&sdma 48>; |
---|
638 | | - dma-names = "tx", "rx"; |
---|
639 | | - }; |
---|
640 | | - |
---|
641 | | - mmc3: mmc@480ad000 { |
---|
642 | | - compatible = "ti,omap4-hsmmc"; |
---|
643 | | - reg = <0x480ad000 0x400>; |
---|
644 | | - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
---|
645 | | - ti,hwmods = "mmc3"; |
---|
646 | | - ti,needs-special-reset; |
---|
647 | | - dmas = <&sdma 77>, <&sdma 78>; |
---|
648 | | - dma-names = "tx", "rx"; |
---|
649 | | - }; |
---|
650 | | - |
---|
651 | | - mmc4: mmc@480d1000 { |
---|
652 | | - compatible = "ti,omap4-hsmmc"; |
---|
653 | | - reg = <0x480d1000 0x400>; |
---|
654 | | - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
---|
655 | | - ti,hwmods = "mmc4"; |
---|
656 | | - ti,needs-special-reset; |
---|
657 | | - dmas = <&sdma 57>, <&sdma 58>; |
---|
658 | | - dma-names = "tx", "rx"; |
---|
659 | | - }; |
---|
660 | | - |
---|
661 | | - mmc5: mmc@480d5000 { |
---|
662 | | - compatible = "ti,omap4-hsmmc"; |
---|
663 | | - reg = <0x480d5000 0x400>; |
---|
664 | | - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
---|
665 | | - ti,hwmods = "mmc5"; |
---|
666 | | - ti,needs-special-reset; |
---|
667 | | - dmas = <&sdma 59>, <&sdma 60>; |
---|
668 | | - dma-names = "tx", "rx"; |
---|
669 | | - }; |
---|
670 | | - |
---|
671 | | - mmu_dsp: mmu@4a066000 { |
---|
672 | | - compatible = "ti,omap4-iommu"; |
---|
673 | | - reg = <0x4a066000 0x100>; |
---|
674 | | - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
---|
675 | | - ti,hwmods = "mmu_dsp"; |
---|
676 | | - #iommu-cells = <0>; |
---|
677 | | - }; |
---|
678 | | - |
---|
679 | | - mmu_ipu: mmu@55082000 { |
---|
680 | | - compatible = "ti,omap4-iommu"; |
---|
681 | | - reg = <0x55082000 0x100>; |
---|
682 | | - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
---|
683 | | - ti,hwmods = "mmu_ipu"; |
---|
684 | | - #iommu-cells = <0>; |
---|
685 | | - ti,iommu-bus-err-back; |
---|
686 | | - }; |
---|
687 | | - |
---|
688 | | - keypad: keypad@4ae1c000 { |
---|
689 | | - compatible = "ti,omap4-keypad"; |
---|
690 | | - reg = <0x4ae1c000 0x400>; |
---|
691 | | - ti,hwmods = "kbd"; |
---|
692 | | - }; |
---|
693 | | - |
---|
694 | | - mcpdm: mcpdm@40132000 { |
---|
695 | | - compatible = "ti,omap4-mcpdm"; |
---|
696 | | - reg = <0x40132000 0x7f>, /* MPU private access */ |
---|
697 | | - <0x49032000 0x7f>; /* L3 Interconnect */ |
---|
698 | | - reg-names = "mpu", "dma"; |
---|
699 | | - interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
---|
700 | | - ti,hwmods = "mcpdm"; |
---|
701 | | - dmas = <&sdma 65>, |
---|
702 | | - <&sdma 66>; |
---|
703 | | - dma-names = "up_link", "dn_link"; |
---|
704 | | - status = "disabled"; |
---|
705 | | - }; |
---|
706 | | - |
---|
707 | | - dmic: dmic@4012e000 { |
---|
708 | | - compatible = "ti,omap4-dmic"; |
---|
709 | | - reg = <0x4012e000 0x7f>, /* MPU private access */ |
---|
710 | | - <0x4902e000 0x7f>; /* L3 Interconnect */ |
---|
711 | | - reg-names = "mpu", "dma"; |
---|
712 | | - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
---|
713 | | - ti,hwmods = "dmic"; |
---|
714 | | - dmas = <&sdma 67>; |
---|
715 | | - dma-names = "up_link"; |
---|
716 | | - status = "disabled"; |
---|
717 | | - }; |
---|
718 | | - |
---|
719 | | - mcbsp1: mcbsp@40122000 { |
---|
720 | | - compatible = "ti,omap4-mcbsp"; |
---|
721 | | - reg = <0x40122000 0xff>, /* MPU private access */ |
---|
722 | | - <0x49022000 0xff>; /* L3 Interconnect */ |
---|
723 | | - reg-names = "mpu", "dma"; |
---|
724 | | - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; |
---|
725 | | - interrupt-names = "common"; |
---|
726 | | - ti,buffer-size = <128>; |
---|
727 | | - ti,hwmods = "mcbsp1"; |
---|
728 | | - dmas = <&sdma 33>, |
---|
729 | | - <&sdma 34>; |
---|
730 | | - dma-names = "tx", "rx"; |
---|
731 | | - status = "disabled"; |
---|
732 | | - }; |
---|
733 | | - |
---|
734 | | - mcbsp2: mcbsp@40124000 { |
---|
735 | | - compatible = "ti,omap4-mcbsp"; |
---|
736 | | - reg = <0x40124000 0xff>, /* MPU private access */ |
---|
737 | | - <0x49024000 0xff>; /* L3 Interconnect */ |
---|
738 | | - reg-names = "mpu", "dma"; |
---|
739 | | - interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
---|
740 | | - interrupt-names = "common"; |
---|
741 | | - ti,buffer-size = <128>; |
---|
742 | | - ti,hwmods = "mcbsp2"; |
---|
743 | | - dmas = <&sdma 17>, |
---|
744 | | - <&sdma 18>; |
---|
745 | | - dma-names = "tx", "rx"; |
---|
746 | | - status = "disabled"; |
---|
747 | | - }; |
---|
748 | | - |
---|
749 | | - mcbsp3: mcbsp@40126000 { |
---|
750 | | - compatible = "ti,omap4-mcbsp"; |
---|
751 | | - reg = <0x40126000 0xff>, /* MPU private access */ |
---|
752 | | - <0x49026000 0xff>; /* L3 Interconnect */ |
---|
753 | | - reg-names = "mpu", "dma"; |
---|
754 | | - interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
---|
755 | | - interrupt-names = "common"; |
---|
756 | | - ti,buffer-size = <128>; |
---|
757 | | - ti,hwmods = "mcbsp3"; |
---|
758 | | - dmas = <&sdma 19>, |
---|
759 | | - <&sdma 20>; |
---|
760 | | - dma-names = "tx", "rx"; |
---|
761 | | - status = "disabled"; |
---|
762 | | - }; |
---|
763 | | - |
---|
764 | | - mailbox: mailbox@4a0f4000 { |
---|
765 | | - compatible = "ti,omap4-mailbox"; |
---|
766 | | - reg = <0x4a0f4000 0x200>; |
---|
767 | | - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
---|
768 | | - ti,hwmods = "mailbox"; |
---|
769 | | - #mbox-cells = <1>; |
---|
770 | | - ti,mbox-num-users = <3>; |
---|
771 | | - ti,mbox-num-fifos = <8>; |
---|
772 | | - mbox_ipu: mbox_ipu { |
---|
773 | | - ti,mbox-tx = <0 0 0>; |
---|
774 | | - ti,mbox-rx = <1 0 0>; |
---|
775 | | - }; |
---|
776 | | - mbox_dsp: mbox_dsp { |
---|
777 | | - ti,mbox-tx = <3 0 0>; |
---|
778 | | - ti,mbox-rx = <2 0 0>; |
---|
779 | | - }; |
---|
780 | | - }; |
---|
781 | | - |
---|
782 | | - timer1: timer@4ae18000 { |
---|
783 | | - compatible = "ti,omap5430-timer"; |
---|
784 | | - reg = <0x4ae18000 0x80>; |
---|
785 | | - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
---|
786 | | - ti,hwmods = "timer1"; |
---|
787 | | - ti,timer-alwon; |
---|
788 | | - clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; |
---|
| 197 | + target-module@55082000 { |
---|
| 198 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 199 | + reg = <0x55082000 0x4>, |
---|
| 200 | + <0x55082010 0x4>, |
---|
| 201 | + <0x55082014 0x4>; |
---|
| 202 | + reg-names = "rev", "sysc", "syss"; |
---|
| 203 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 204 | + <SYSC_IDLE_NO>, |
---|
| 205 | + <SYSC_IDLE_SMART>; |
---|
| 206 | + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
---|
| 207 | + SYSC_OMAP2_SOFTRESET | |
---|
| 208 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 209 | + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; |
---|
789 | 210 | clock-names = "fck"; |
---|
| 211 | + resets = <&prm_core 2>; |
---|
| 212 | + reset-names = "rstctrl"; |
---|
| 213 | + ranges = <0x0 0x55082000 0x100>; |
---|
| 214 | + #size-cells = <1>; |
---|
| 215 | + #address-cells = <1>; |
---|
| 216 | + |
---|
| 217 | + mmu_ipu: mmu@0 { |
---|
| 218 | + compatible = "ti,omap4-iommu"; |
---|
| 219 | + reg = <0x0 0x100>; |
---|
| 220 | + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 221 | + #iommu-cells = <0>; |
---|
| 222 | + ti,iommu-bus-err-back; |
---|
| 223 | + }; |
---|
790 | 224 | }; |
---|
791 | 225 | |
---|
792 | | - timer2: timer@48032000 { |
---|
793 | | - compatible = "ti,omap5430-timer"; |
---|
794 | | - reg = <0x48032000 0x80>; |
---|
795 | | - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
---|
796 | | - ti,hwmods = "timer2"; |
---|
| 226 | + dsp: dsp { |
---|
| 227 | + compatible = "ti,omap5-dsp"; |
---|
| 228 | + ti,bootreg = <&scm_conf 0x304 0>; |
---|
| 229 | + iommus = <&mmu_dsp>; |
---|
| 230 | + resets = <&prm_dsp 0>; |
---|
| 231 | + clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>; |
---|
| 232 | + firmware-name = "omap5-dsp-fw.xe64T"; |
---|
| 233 | + mboxes = <&mailbox &mbox_dsp>; |
---|
| 234 | + status = "disabled"; |
---|
797 | 235 | }; |
---|
798 | 236 | |
---|
799 | | - timer3: timer@48034000 { |
---|
800 | | - compatible = "ti,omap5430-timer"; |
---|
801 | | - reg = <0x48034000 0x80>; |
---|
802 | | - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
---|
803 | | - ti,hwmods = "timer3"; |
---|
804 | | - }; |
---|
805 | | - |
---|
806 | | - timer4: timer@48036000 { |
---|
807 | | - compatible = "ti,omap5430-timer"; |
---|
808 | | - reg = <0x48036000 0x80>; |
---|
809 | | - interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; |
---|
810 | | - ti,hwmods = "timer4"; |
---|
811 | | - }; |
---|
812 | | - |
---|
813 | | - timer5: timer@40138000 { |
---|
814 | | - compatible = "ti,omap5430-timer"; |
---|
815 | | - reg = <0x40138000 0x80>, |
---|
816 | | - <0x49038000 0x80>; |
---|
817 | | - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; |
---|
818 | | - ti,hwmods = "timer5"; |
---|
819 | | - ti,timer-dsp; |
---|
820 | | - ti,timer-pwm; |
---|
821 | | - }; |
---|
822 | | - |
---|
823 | | - timer6: timer@4013a000 { |
---|
824 | | - compatible = "ti,omap5430-timer"; |
---|
825 | | - reg = <0x4013a000 0x80>, |
---|
826 | | - <0x4903a000 0x80>; |
---|
827 | | - interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; |
---|
828 | | - ti,hwmods = "timer6"; |
---|
829 | | - ti,timer-dsp; |
---|
830 | | - ti,timer-pwm; |
---|
831 | | - }; |
---|
832 | | - |
---|
833 | | - timer7: timer@4013c000 { |
---|
834 | | - compatible = "ti,omap5430-timer"; |
---|
835 | | - reg = <0x4013c000 0x80>, |
---|
836 | | - <0x4903c000 0x80>; |
---|
837 | | - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; |
---|
838 | | - ti,hwmods = "timer7"; |
---|
839 | | - ti,timer-dsp; |
---|
840 | | - }; |
---|
841 | | - |
---|
842 | | - timer8: timer@4013e000 { |
---|
843 | | - compatible = "ti,omap5430-timer"; |
---|
844 | | - reg = <0x4013e000 0x80>, |
---|
845 | | - <0x4903e000 0x80>; |
---|
846 | | - interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
---|
847 | | - ti,hwmods = "timer8"; |
---|
848 | | - ti,timer-dsp; |
---|
849 | | - ti,timer-pwm; |
---|
850 | | - }; |
---|
851 | | - |
---|
852 | | - timer9: timer@4803e000 { |
---|
853 | | - compatible = "ti,omap5430-timer"; |
---|
854 | | - reg = <0x4803e000 0x80>; |
---|
855 | | - interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; |
---|
856 | | - ti,hwmods = "timer9"; |
---|
857 | | - ti,timer-pwm; |
---|
858 | | - }; |
---|
859 | | - |
---|
860 | | - timer10: timer@48086000 { |
---|
861 | | - compatible = "ti,omap5430-timer"; |
---|
862 | | - reg = <0x48086000 0x80>; |
---|
863 | | - interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
---|
864 | | - ti,hwmods = "timer10"; |
---|
865 | | - ti,timer-pwm; |
---|
866 | | - }; |
---|
867 | | - |
---|
868 | | - timer11: timer@48088000 { |
---|
869 | | - compatible = "ti,omap5430-timer"; |
---|
870 | | - reg = <0x48088000 0x80>; |
---|
871 | | - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
---|
872 | | - ti,hwmods = "timer11"; |
---|
873 | | - ti,timer-pwm; |
---|
874 | | - }; |
---|
875 | | - |
---|
876 | | - wdt2: wdt@4ae14000 { |
---|
877 | | - compatible = "ti,omap5-wdt", "ti,omap3-wdt"; |
---|
878 | | - reg = <0x4ae14000 0x80>; |
---|
879 | | - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
---|
880 | | - ti,hwmods = "wd_timer2"; |
---|
| 237 | + ipu: ipu@55020000 { |
---|
| 238 | + compatible = "ti,omap5-ipu"; |
---|
| 239 | + reg = <0x55020000 0x10000>; |
---|
| 240 | + reg-names = "l2ram"; |
---|
| 241 | + iommus = <&mmu_ipu>; |
---|
| 242 | + resets = <&prm_core 0>, <&prm_core 1>; |
---|
| 243 | + clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>; |
---|
| 244 | + firmware-name = "omap5-ipu-fw.xem4"; |
---|
| 245 | + mboxes = <&mailbox &mbox_ipu>; |
---|
| 246 | + status = "disabled"; |
---|
881 | 247 | }; |
---|
882 | 248 | |
---|
883 | 249 | dmm@4e000000 { |
---|
.. | .. |
---|
911 | 277 | hw-caps-temp-alert; |
---|
912 | 278 | }; |
---|
913 | 279 | |
---|
914 | | - usb3: omap_dwc3@4a020000 { |
---|
915 | | - compatible = "ti,dwc3"; |
---|
916 | | - ti,hwmods = "usb_otg_ss"; |
---|
917 | | - reg = <0x4a020000 0x10000>; |
---|
918 | | - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 280 | + aes1_target: target-module@4b501000 { |
---|
| 281 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 282 | + reg = <0x4b501080 0x4>, |
---|
| 283 | + <0x4b501084 0x4>, |
---|
| 284 | + <0x4b501088 0x4>; |
---|
| 285 | + reg-names = "rev", "sysc", "syss"; |
---|
| 286 | + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
---|
| 287 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 288 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 289 | + <SYSC_IDLE_NO>, |
---|
| 290 | + <SYSC_IDLE_SMART>, |
---|
| 291 | + <SYSC_IDLE_SMART_WKUP>; |
---|
| 292 | + ti,syss-mask = <1>; |
---|
| 293 | + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ |
---|
| 294 | + clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>; |
---|
| 295 | + clock-names = "fck"; |
---|
919 | 296 | #address-cells = <1>; |
---|
920 | 297 | #size-cells = <1>; |
---|
921 | | - utmi-mode = <2>; |
---|
922 | | - ranges; |
---|
923 | | - dwc3: dwc3@4a030000 { |
---|
924 | | - compatible = "snps,dwc3"; |
---|
925 | | - reg = <0x4a030000 0x10000>; |
---|
926 | | - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
---|
927 | | - <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |
---|
928 | | - <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
---|
929 | | - interrupt-names = "peripheral", |
---|
930 | | - "host", |
---|
931 | | - "otg"; |
---|
932 | | - phys = <&usb2_phy>, <&usb3_phy>; |
---|
933 | | - phy-names = "usb2-phy", "usb3-phy"; |
---|
934 | | - dr_mode = "peripheral"; |
---|
| 298 | + ranges = <0x0 0x4b501000 0x1000>; |
---|
| 299 | + |
---|
| 300 | + aes1: aes@0 { |
---|
| 301 | + compatible = "ti,omap4-aes"; |
---|
| 302 | + reg = <0 0xa0>; |
---|
| 303 | + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 304 | + dmas = <&sdma 111>, <&sdma 110>; |
---|
| 305 | + dma-names = "tx", "rx"; |
---|
935 | 306 | }; |
---|
936 | 307 | }; |
---|
937 | 308 | |
---|
938 | | - ocp2scp@4a080000 { |
---|
939 | | - compatible = "ti,omap-ocp2scp"; |
---|
| 309 | + aes2_target: target-module@4b701000 { |
---|
| 310 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 311 | + reg = <0x4b701080 0x4>, |
---|
| 312 | + <0x4b701084 0x4>, |
---|
| 313 | + <0x4b701088 0x4>; |
---|
| 314 | + reg-names = "rev", "sysc", "syss"; |
---|
| 315 | + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
---|
| 316 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 317 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 318 | + <SYSC_IDLE_NO>, |
---|
| 319 | + <SYSC_IDLE_SMART>, |
---|
| 320 | + <SYSC_IDLE_SMART_WKUP>; |
---|
| 321 | + ti,syss-mask = <1>; |
---|
| 322 | + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ |
---|
| 323 | + clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>; |
---|
| 324 | + clock-names = "fck"; |
---|
940 | 325 | #address-cells = <1>; |
---|
941 | 326 | #size-cells = <1>; |
---|
942 | | - reg = <0x4a080000 0x20>; |
---|
943 | | - ranges; |
---|
944 | | - ti,hwmods = "ocp2scp1"; |
---|
945 | | - usb2_phy: usb2phy@4a084000 { |
---|
946 | | - compatible = "ti,omap-usb2"; |
---|
947 | | - reg = <0x4a084000 0x7c>; |
---|
948 | | - syscon-phy-power = <&scm_conf 0x300>; |
---|
949 | | - clocks = <&usb_phy_cm_clk32k>, |
---|
950 | | - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; |
---|
951 | | - clock-names = "wkupclk", "refclk"; |
---|
952 | | - #phy-cells = <0>; |
---|
953 | | - }; |
---|
| 327 | + ranges = <0x0 0x4b701000 0x1000>; |
---|
954 | 328 | |
---|
955 | | - usb3_phy: usb3phy@4a084400 { |
---|
956 | | - compatible = "ti,omap-usb3"; |
---|
957 | | - reg = <0x4a084400 0x80>, |
---|
958 | | - <0x4a084800 0x64>, |
---|
959 | | - <0x4a084c00 0x40>; |
---|
960 | | - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
---|
961 | | - syscon-phy-power = <&scm_conf 0x370>; |
---|
962 | | - clocks = <&usb_phy_cm_clk32k>, |
---|
963 | | - <&sys_clkin>, |
---|
964 | | - <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>; |
---|
965 | | - clock-names = "wkupclk", |
---|
966 | | - "sysclk", |
---|
967 | | - "refclk"; |
---|
968 | | - #phy-cells = <0>; |
---|
| 329 | + aes2: aes@0 { |
---|
| 330 | + compatible = "ti,omap4-aes"; |
---|
| 331 | + reg = <0 0xa0>; |
---|
| 332 | + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 333 | + dmas = <&sdma 114>, <&sdma 113>; |
---|
| 334 | + dma-names = "tx", "rx"; |
---|
969 | 335 | }; |
---|
970 | 336 | }; |
---|
971 | 337 | |
---|
972 | | - usbhstll: usbhstll@4a062000 { |
---|
973 | | - compatible = "ti,usbhs-tll"; |
---|
974 | | - reg = <0x4a062000 0x1000>; |
---|
975 | | - interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
---|
976 | | - ti,hwmods = "usb_tll_hs"; |
---|
977 | | - }; |
---|
978 | | - |
---|
979 | | - usbhshost: usbhshost@4a064000 { |
---|
980 | | - compatible = "ti,usbhs-host"; |
---|
981 | | - reg = <0x4a064000 0x800>; |
---|
982 | | - ti,hwmods = "usb_host_hs"; |
---|
| 338 | + sham_target: target-module@4b100000 { |
---|
| 339 | + compatible = "ti,sysc-omap3-sham", "ti,sysc"; |
---|
| 340 | + reg = <0x4b100100 0x4>, |
---|
| 341 | + <0x4b100110 0x4>, |
---|
| 342 | + <0x4b100114 0x4>; |
---|
| 343 | + reg-names = "rev", "sysc", "syss"; |
---|
| 344 | + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
---|
| 345 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 346 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 347 | + <SYSC_IDLE_NO>, |
---|
| 348 | + <SYSC_IDLE_SMART>; |
---|
| 349 | + ti,syss-mask = <1>; |
---|
| 350 | + /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */ |
---|
| 351 | + clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>; |
---|
| 352 | + clock-names = "fck"; |
---|
983 | 353 | #address-cells = <1>; |
---|
984 | 354 | #size-cells = <1>; |
---|
985 | | - ranges; |
---|
986 | | - clocks = <&l3init_60m_fclk>, |
---|
987 | | - <&xclk60mhsp1_ck>, |
---|
988 | | - <&xclk60mhsp2_ck>; |
---|
989 | | - clock-names = "refclk_60m_int", |
---|
990 | | - "refclk_60m_ext_p1", |
---|
991 | | - "refclk_60m_ext_p2"; |
---|
| 355 | + ranges = <0x0 0x4b100000 0x1000>; |
---|
992 | 356 | |
---|
993 | | - usbhsohci: ohci@4a064800 { |
---|
994 | | - compatible = "ti,ohci-omap3"; |
---|
995 | | - reg = <0x4a064800 0x400>; |
---|
996 | | - interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
---|
997 | | - remote-wakeup-connected; |
---|
998 | | - }; |
---|
999 | | - |
---|
1000 | | - usbhsehci: ehci@4a064c00 { |
---|
1001 | | - compatible = "ti,ehci-omap"; |
---|
1002 | | - reg = <0x4a064c00 0x400>; |
---|
1003 | | - interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 357 | + sham: sham@0 { |
---|
| 358 | + compatible = "ti,omap4-sham"; |
---|
| 359 | + reg = <0 0x300>; |
---|
| 360 | + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 361 | + dmas = <&sdma 119>; |
---|
| 362 | + dma-names = "rx"; |
---|
1004 | 363 | }; |
---|
1005 | 364 | }; |
---|
1006 | 365 | |
---|
.. | .. |
---|
1016 | 375 | }; |
---|
1017 | 376 | |
---|
1018 | 377 | /* OCP2SCP3 */ |
---|
1019 | | - ocp2scp@4a090000 { |
---|
1020 | | - compatible = "ti,omap-ocp2scp"; |
---|
1021 | | - #address-cells = <1>; |
---|
1022 | | - #size-cells = <1>; |
---|
1023 | | - reg = <0x4a090000 0x20>; |
---|
1024 | | - ranges; |
---|
1025 | | - ti,hwmods = "ocp2scp3"; |
---|
1026 | | - sata_phy: phy@4a096000 { |
---|
1027 | | - compatible = "ti,phy-pipe3-sata"; |
---|
1028 | | - reg = <0x4A096000 0x80>, /* phy_rx */ |
---|
1029 | | - <0x4A096400 0x64>, /* phy_tx */ |
---|
1030 | | - <0x4A096800 0x40>; /* pll_ctrl */ |
---|
1031 | | - reg-names = "phy_rx", "phy_tx", "pll_ctrl"; |
---|
1032 | | - syscon-phy-power = <&scm_conf 0x374>; |
---|
1033 | | - clocks = <&sys_clkin>, |
---|
1034 | | - <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>; |
---|
1035 | | - clock-names = "sysclk", "refclk"; |
---|
1036 | | - #phy-cells = <0>; |
---|
1037 | | - }; |
---|
1038 | | - }; |
---|
1039 | | - |
---|
1040 | 378 | sata: sata@4a141100 { |
---|
1041 | 379 | compatible = "snps,dwc-ahci"; |
---|
1042 | 380 | reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; |
---|
.. | .. |
---|
1048 | 386 | ports-implemented = <0x1>; |
---|
1049 | 387 | }; |
---|
1050 | 388 | |
---|
1051 | | - dss: dss@58000000 { |
---|
1052 | | - compatible = "ti,omap5-dss"; |
---|
1053 | | - reg = <0x58000000 0x80>; |
---|
1054 | | - status = "disabled"; |
---|
1055 | | - ti,hwmods = "dss_core"; |
---|
1056 | | - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; |
---|
| 389 | + target-module@56000000 { |
---|
| 390 | + compatible = "ti,sysc-omap4", "ti,sysc"; |
---|
| 391 | + reg = <0x5600fe00 0x4>, |
---|
| 392 | + <0x5600fe10 0x4>; |
---|
| 393 | + reg-names = "rev", "sysc"; |
---|
| 394 | + ti,sysc-midle = <SYSC_IDLE_FORCE>, |
---|
| 395 | + <SYSC_IDLE_NO>, |
---|
| 396 | + <SYSC_IDLE_SMART>; |
---|
| 397 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 398 | + <SYSC_IDLE_NO>, |
---|
| 399 | + <SYSC_IDLE_SMART>; |
---|
| 400 | + clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>; |
---|
1057 | 401 | clock-names = "fck"; |
---|
1058 | 402 | #address-cells = <1>; |
---|
1059 | 403 | #size-cells = <1>; |
---|
1060 | | - ranges; |
---|
| 404 | + ranges = <0 0x56000000 0x2000000>; |
---|
1061 | 405 | |
---|
1062 | | - dispc@58001000 { |
---|
1063 | | - compatible = "ti,omap5-dispc"; |
---|
1064 | | - reg = <0x58001000 0x1000>; |
---|
1065 | | - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
---|
1066 | | - ti,hwmods = "dss_dispc"; |
---|
| 406 | + /* |
---|
| 407 | + * Closed source PowerVR driver, no child device |
---|
| 408 | + * binding or driver in mainline |
---|
| 409 | + */ |
---|
| 410 | + }; |
---|
| 411 | + |
---|
| 412 | + target-module@58000000 { |
---|
| 413 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 414 | + reg = <0x58000000 4>, |
---|
| 415 | + <0x58000014 4>; |
---|
| 416 | + reg-names = "rev", "syss"; |
---|
| 417 | + ti,syss-mask = <1>; |
---|
| 418 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>, |
---|
| 419 | + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, |
---|
| 420 | + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>, |
---|
| 421 | + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>; |
---|
| 422 | + clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk"; |
---|
| 423 | + #address-cells = <1>; |
---|
| 424 | + #size-cells = <1>; |
---|
| 425 | + ranges = <0 0x58000000 0x1000000>; |
---|
| 426 | + |
---|
| 427 | + dss: dss@0 { |
---|
| 428 | + compatible = "ti,omap5-dss"; |
---|
| 429 | + reg = <0 0x80>; |
---|
| 430 | + status = "disabled"; |
---|
1067 | 431 | clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; |
---|
1068 | 432 | clock-names = "fck"; |
---|
1069 | | - }; |
---|
| 433 | + #address-cells = <1>; |
---|
| 434 | + #size-cells = <1>; |
---|
| 435 | + ranges = <0 0 0x1000000>; |
---|
1070 | 436 | |
---|
1071 | | - rfbi: encoder@58002000 { |
---|
1072 | | - compatible = "ti,omap5-rfbi"; |
---|
1073 | | - reg = <0x58002000 0x100>; |
---|
1074 | | - status = "disabled"; |
---|
1075 | | - ti,hwmods = "dss_rfbi"; |
---|
1076 | | - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; |
---|
1077 | | - clock-names = "fck", "ick"; |
---|
1078 | | - }; |
---|
| 437 | + target-module@1000 { |
---|
| 438 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 439 | + reg = <0x1000 0x4>, |
---|
| 440 | + <0x1010 0x4>, |
---|
| 441 | + <0x1014 0x4>; |
---|
| 442 | + reg-names = "rev", "sysc", "syss"; |
---|
| 443 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 444 | + <SYSC_IDLE_NO>, |
---|
| 445 | + <SYSC_IDLE_SMART>; |
---|
| 446 | + ti,sysc-midle = <SYSC_IDLE_FORCE>, |
---|
| 447 | + <SYSC_IDLE_NO>, |
---|
| 448 | + <SYSC_IDLE_SMART>; |
---|
| 449 | + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
---|
| 450 | + SYSC_OMAP2_ENAWAKEUP | |
---|
| 451 | + SYSC_OMAP2_SOFTRESET | |
---|
| 452 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 453 | + ti,syss-mask = <1>; |
---|
| 454 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; |
---|
| 455 | + clock-names = "fck"; |
---|
| 456 | + #address-cells = <1>; |
---|
| 457 | + #size-cells = <1>; |
---|
| 458 | + ranges = <0 0x1000 0x1000>; |
---|
1079 | 459 | |
---|
1080 | | - dsi1: encoder@58004000 { |
---|
1081 | | - compatible = "ti,omap5-dsi"; |
---|
1082 | | - reg = <0x58004000 0x200>, |
---|
1083 | | - <0x58004200 0x40>, |
---|
1084 | | - <0x58004300 0x40>; |
---|
1085 | | - reg-names = "proto", "phy", "pll"; |
---|
1086 | | - interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
---|
1087 | | - status = "disabled"; |
---|
1088 | | - ti,hwmods = "dss_dsi1"; |
---|
1089 | | - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, |
---|
1090 | | - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; |
---|
1091 | | - clock-names = "fck", "sys_clk"; |
---|
1092 | | - }; |
---|
| 460 | + dispc@0 { |
---|
| 461 | + compatible = "ti,omap5-dispc"; |
---|
| 462 | + reg = <0 0x1000>; |
---|
| 463 | + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 464 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; |
---|
| 465 | + clock-names = "fck"; |
---|
| 466 | + }; |
---|
| 467 | + }; |
---|
1093 | 468 | |
---|
1094 | | - dsi2: encoder@58005000 { |
---|
1095 | | - compatible = "ti,omap5-dsi"; |
---|
1096 | | - reg = <0x58009000 0x200>, |
---|
1097 | | - <0x58009200 0x40>, |
---|
1098 | | - <0x58009300 0x40>; |
---|
1099 | | - reg-names = "proto", "phy", "pll"; |
---|
1100 | | - interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
---|
1101 | | - status = "disabled"; |
---|
1102 | | - ti,hwmods = "dss_dsi2"; |
---|
1103 | | - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, |
---|
1104 | | - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; |
---|
1105 | | - clock-names = "fck", "sys_clk"; |
---|
1106 | | - }; |
---|
| 469 | + target-module@2000 { |
---|
| 470 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 471 | + reg = <0x2000 0x4>, |
---|
| 472 | + <0x2010 0x4>, |
---|
| 473 | + <0x2014 0x4>; |
---|
| 474 | + reg-names = "rev", "sysc", "syss"; |
---|
| 475 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 476 | + <SYSC_IDLE_NO>, |
---|
| 477 | + <SYSC_IDLE_SMART>; |
---|
| 478 | + ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET | |
---|
| 479 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 480 | + ti,syss-mask = <1>; |
---|
| 481 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; |
---|
| 482 | + clock-names = "fck"; |
---|
| 483 | + #address-cells = <1>; |
---|
| 484 | + #size-cells = <1>; |
---|
| 485 | + ranges = <0 0x2000 0x1000>; |
---|
1107 | 486 | |
---|
1108 | | - hdmi: encoder@58060000 { |
---|
1109 | | - compatible = "ti,omap5-hdmi"; |
---|
1110 | | - reg = <0x58040000 0x200>, |
---|
1111 | | - <0x58040200 0x80>, |
---|
1112 | | - <0x58040300 0x80>, |
---|
1113 | | - <0x58060000 0x19000>; |
---|
1114 | | - reg-names = "wp", "pll", "phy", "core"; |
---|
1115 | | - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
---|
1116 | | - status = "disabled"; |
---|
1117 | | - ti,hwmods = "dss_hdmi"; |
---|
1118 | | - clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, |
---|
1119 | | - <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; |
---|
1120 | | - clock-names = "fck", "sys_clk"; |
---|
1121 | | - dmas = <&sdma 76>; |
---|
1122 | | - dma-names = "audio_tx"; |
---|
| 487 | + rfbi: encoder@0 { |
---|
| 488 | + compatible = "ti,omap5-rfbi"; |
---|
| 489 | + reg = <0 0x100>; |
---|
| 490 | + status = "disabled"; |
---|
| 491 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>; |
---|
| 492 | + clock-names = "fck", "ick"; |
---|
| 493 | + }; |
---|
| 494 | + }; |
---|
| 495 | + |
---|
| 496 | + target-module@4000 { |
---|
| 497 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 498 | + reg = <0x4000 0x4>, |
---|
| 499 | + <0x4010 0x4>, |
---|
| 500 | + <0x4014 0x4>; |
---|
| 501 | + reg-names = "rev", "sysc", "syss"; |
---|
| 502 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 503 | + <SYSC_IDLE_NO>, |
---|
| 504 | + <SYSC_IDLE_SMART>; |
---|
| 505 | + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
---|
| 506 | + SYSC_OMAP2_ENAWAKEUP | |
---|
| 507 | + SYSC_OMAP2_SOFTRESET | |
---|
| 508 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 509 | + ti,syss-mask = <1>; |
---|
| 510 | + #address-cells = <1>; |
---|
| 511 | + #size-cells = <1>; |
---|
| 512 | + ranges = <0 0x4000 0x1000>; |
---|
| 513 | + |
---|
| 514 | + dsi1: encoder@0 { |
---|
| 515 | + compatible = "ti,omap5-dsi"; |
---|
| 516 | + reg = <0 0x200>, |
---|
| 517 | + <0x200 0x40>, |
---|
| 518 | + <0x300 0x40>; |
---|
| 519 | + reg-names = "proto", "phy", "pll"; |
---|
| 520 | + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 521 | + status = "disabled"; |
---|
| 522 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, |
---|
| 523 | + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; |
---|
| 524 | + clock-names = "fck", "sys_clk"; |
---|
| 525 | + }; |
---|
| 526 | + }; |
---|
| 527 | + |
---|
| 528 | + target-module@9000 { |
---|
| 529 | + compatible = "ti,sysc-omap2", "ti,sysc"; |
---|
| 530 | + reg = <0x9000 0x4>, |
---|
| 531 | + <0x9010 0x4>, |
---|
| 532 | + <0x9014 0x4>; |
---|
| 533 | + reg-names = "rev", "sysc", "syss"; |
---|
| 534 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 535 | + <SYSC_IDLE_NO>, |
---|
| 536 | + <SYSC_IDLE_SMART>; |
---|
| 537 | + ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY | |
---|
| 538 | + SYSC_OMAP2_ENAWAKEUP | |
---|
| 539 | + SYSC_OMAP2_SOFTRESET | |
---|
| 540 | + SYSC_OMAP2_AUTOIDLE)>; |
---|
| 541 | + ti,syss-mask = <1>; |
---|
| 542 | + #address-cells = <1>; |
---|
| 543 | + #size-cells = <1>; |
---|
| 544 | + ranges = <0 0x9000 0x1000>; |
---|
| 545 | + |
---|
| 546 | + dsi2: encoder@0 { |
---|
| 547 | + compatible = "ti,omap5-dsi"; |
---|
| 548 | + reg = <0 0x200>, |
---|
| 549 | + <0x200 0x40>, |
---|
| 550 | + <0x300 0x40>; |
---|
| 551 | + reg-names = "proto", "phy", "pll"; |
---|
| 552 | + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 553 | + status = "disabled"; |
---|
| 554 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, |
---|
| 555 | + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; |
---|
| 556 | + clock-names = "fck", "sys_clk"; |
---|
| 557 | + }; |
---|
| 558 | + }; |
---|
| 559 | + |
---|
| 560 | + target-module@40000 { |
---|
| 561 | + compatible = "ti,sysc-omap4", "ti,sysc"; |
---|
| 562 | + reg = <0x40000 0x4>, |
---|
| 563 | + <0x40010 0x4>; |
---|
| 564 | + reg-names = "rev", "sysc"; |
---|
| 565 | + ti,sysc-sidle = <SYSC_IDLE_FORCE>, |
---|
| 566 | + <SYSC_IDLE_NO>, |
---|
| 567 | + <SYSC_IDLE_SMART>, |
---|
| 568 | + <SYSC_IDLE_SMART_WKUP>; |
---|
| 569 | + ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>; |
---|
| 570 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, |
---|
| 571 | + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>; |
---|
| 572 | + clock-names = "fck", "dss_clk"; |
---|
| 573 | + #address-cells = <1>; |
---|
| 574 | + #size-cells = <1>; |
---|
| 575 | + ranges = <0 0x40000 0x40000>; |
---|
| 576 | + |
---|
| 577 | + hdmi: encoder@0 { |
---|
| 578 | + compatible = "ti,omap5-hdmi"; |
---|
| 579 | + reg = <0 0x200>, |
---|
| 580 | + <0x200 0x80>, |
---|
| 581 | + <0x300 0x80>, |
---|
| 582 | + <0x20000 0x19000>; |
---|
| 583 | + reg-names = "wp", "pll", "phy", "core"; |
---|
| 584 | + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
---|
| 585 | + status = "disabled"; |
---|
| 586 | + clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>, |
---|
| 587 | + <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>; |
---|
| 588 | + clock-names = "fck", "sys_clk"; |
---|
| 589 | + dmas = <&sdma 76>; |
---|
| 590 | + dma-names = "audio_tx"; |
---|
| 591 | + }; |
---|
| 592 | + }; |
---|
1123 | 593 | }; |
---|
1124 | 594 | }; |
---|
1125 | 595 | |
---|
.. | .. |
---|
1190 | 660 | coefficients = <65 (-1791)>; |
---|
1191 | 661 | }; |
---|
1192 | 662 | |
---|
| 663 | +#include "omap5-l4.dtsi" |
---|
1193 | 664 | #include "omap54xx-clocks.dtsi" |
---|
1194 | 665 | |
---|
1195 | 666 | &gpu_thermal { |
---|
.. | .. |
---|
1199 | 670 | &core_thermal { |
---|
1200 | 671 | coefficients = <0 2000>; |
---|
1201 | 672 | }; |
---|
| 673 | + |
---|
| 674 | +#include "omap5-l4-abe.dtsi" |
---|
| 675 | +#include "omap54xx-clocks.dtsi" |
---|
| 676 | + |
---|
| 677 | +&prm { |
---|
| 678 | + prm_dsp: prm@400 { |
---|
| 679 | + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; |
---|
| 680 | + reg = <0x400 0x100>; |
---|
| 681 | + #reset-cells = <1>; |
---|
| 682 | + }; |
---|
| 683 | + |
---|
| 684 | + prm_abe: prm@500 { |
---|
| 685 | + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; |
---|
| 686 | + reg = <0x500 0x100>; |
---|
| 687 | + #power-domain-cells = <0>; |
---|
| 688 | + }; |
---|
| 689 | + |
---|
| 690 | + prm_core: prm@700 { |
---|
| 691 | + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; |
---|
| 692 | + reg = <0x700 0x100>; |
---|
| 693 | + #reset-cells = <1>; |
---|
| 694 | + }; |
---|
| 695 | + |
---|
| 696 | + prm_iva: prm@1200 { |
---|
| 697 | + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; |
---|
| 698 | + reg = <0x1200 0x100>; |
---|
| 699 | + #reset-cells = <1>; |
---|
| 700 | + }; |
---|
| 701 | + |
---|
| 702 | + prm_device: prm@1c00 { |
---|
| 703 | + compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst"; |
---|
| 704 | + reg = <0x1c00 0x100>; |
---|
| 705 | + #reset-cells = <1>; |
---|
| 706 | + }; |
---|
| 707 | +}; |
---|
| 708 | + |
---|
| 709 | +/* Preferred always-on timer for clockevent */ |
---|
| 710 | +&timer1_target { |
---|
| 711 | + ti,no-reset-on-init; |
---|
| 712 | + ti,no-idle; |
---|
| 713 | + timer@0 { |
---|
| 714 | + assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>; |
---|
| 715 | + assigned-clock-parents = <&sys_32k_ck>; |
---|
| 716 | + }; |
---|
| 717 | +}; |
---|