hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/arm/boot/dts/omap5.dtsi
....@@ -1,12 +1,11 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
2
- * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3
+ * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
34 *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License version 2 as
6
- * published by the Free Software Foundation.
75 * Based on "omap4.dtsi"
86 */
97
8
+#include <dt-bindings/bus/ti-sysc.h>
109 #include <dt-bindings/gpio/gpio.h>
1110 #include <dt-bindings/interrupt-controller/arm-gic.h>
1211 #include <dt-bindings/pinctrl/omap.h>
....@@ -37,6 +36,8 @@
3736 serial3 = &uart4;
3837 serial4 = &uart5;
3938 serial5 = &uart6;
39
+ rproc0 = &dsp;
40
+ rproc1 = &ipu;
4041 };
4142
4243 cpus {
....@@ -157,285 +158,21 @@
157158 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
158159 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
159160
160
- l4_cfg: l4@4a000000 {
161
- compatible = "ti,omap5-l4-cfg", "simple-bus";
162
- #address-cells = <1>;
163
- #size-cells = <1>;
164
- ranges = <0 0x4a000000 0x22a000>;
165
-
166
- scm_core: scm@2000 {
167
- compatible = "ti,omap5-scm-core", "simple-bus";
168
- reg = <0x2000 0x1000>;
169
- #address-cells = <1>;
170
- #size-cells = <1>;
171
- ranges = <0 0x2000 0x800>;
172
-
173
- scm_conf: scm_conf@0 {
174
- compatible = "syscon";
175
- reg = <0x0 0x800>;
176
- #address-cells = <1>;
177
- #size-cells = <1>;
178
- };
179
- };
180
-
181
- scm_padconf_core: scm@2800 {
182
- compatible = "ti,omap5-scm-padconf-core",
183
- "simple-bus";
184
- #address-cells = <1>;
185
- #size-cells = <1>;
186
- ranges = <0 0x2800 0x800>;
187
-
188
- omap5_pmx_core: pinmux@40 {
189
- compatible = "ti,omap5-padconf",
190
- "pinctrl-single";
191
- reg = <0x40 0x01b6>;
192
- #address-cells = <1>;
193
- #size-cells = <0>;
194
- #pinctrl-cells = <1>;
195
- #interrupt-cells = <1>;
196
- interrupt-controller;
197
- pinctrl-single,register-width = <16>;
198
- pinctrl-single,function-mask = <0x7fff>;
199
- };
200
-
201
- omap5_padconf_global: omap5_padconf_global@5a0 {
202
- compatible = "syscon",
203
- "simple-bus";
204
- reg = <0x5a0 0xec>;
205
- #address-cells = <1>;
206
- #size-cells = <1>;
207
- ranges = <0 0x5a0 0xec>;
208
-
209
- pbias_regulator: pbias_regulator@60 {
210
- compatible = "ti,pbias-omap5", "ti,pbias-omap";
211
- reg = <0x60 0x4>;
212
- syscon = <&omap5_padconf_global>;
213
- pbias_mmc_reg: pbias_mmc_omap5 {
214
- regulator-name = "pbias_mmc_omap5";
215
- regulator-min-microvolt = <1800000>;
216
- regulator-max-microvolt = <3300000>;
217
- };
218
- };
219
- };
220
- };
221
-
222
- cm_core_aon: cm_core_aon@4000 {
223
- compatible = "ti,omap5-cm-core-aon",
224
- "simple-bus";
225
- reg = <0x4000 0x2000>;
226
- #address-cells = <1>;
227
- #size-cells = <1>;
228
- ranges = <0 0x4000 0x2000>;
229
-
230
- cm_core_aon_clocks: clocks {
231
- #address-cells = <1>;
232
- #size-cells = <0>;
233
- };
234
-
235
- cm_core_aon_clockdomains: clockdomains {
236
- };
237
- };
238
-
239
- cm_core: cm_core@8000 {
240
- compatible = "ti,omap5-cm-core", "simple-bus";
241
- reg = <0x8000 0x3000>;
242
- #address-cells = <1>;
243
- #size-cells = <1>;
244
- ranges = <0 0x8000 0x3000>;
245
-
246
- cm_core_clocks: clocks {
247
- #address-cells = <1>;
248
- #size-cells = <0>;
249
- };
250
-
251
- cm_core_clockdomains: clockdomains {
252
- };
253
- };
161
+ l4_wkup: interconnect@4ae00000 {
254162 };
255163
256
- l4_wkup: l4@4ae00000 {
257
- compatible = "ti,omap5-l4-wkup", "simple-bus";
258
- #address-cells = <1>;
259
- #size-cells = <1>;
260
- ranges = <0 0x4ae00000 0x2b000>;
261
-
262
- counter32k: counter@4000 {
263
- compatible = "ti,omap-counter32k";
264
- reg = <0x4000 0x40>;
265
- ti,hwmods = "counter_32k";
266
- };
267
-
268
- prm: prm@6000 {
269
- compatible = "ti,omap5-prm", "simple-bus";
270
- reg = <0x6000 0x3000>;
271
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
272
- #address-cells = <1>;
273
- #size-cells = <1>;
274
- ranges = <0 0x6000 0x3000>;
275
-
276
- prm_clocks: clocks {
277
- #address-cells = <1>;
278
- #size-cells = <0>;
279
- };
280
-
281
- prm_clockdomains: clockdomains {
282
- };
283
- };
284
-
285
- scrm: scrm@a000 {
286
- compatible = "ti,omap5-scrm";
287
- reg = <0xa000 0x2000>;
288
-
289
- scrm_clocks: clocks {
290
- #address-cells = <1>;
291
- #size-cells = <0>;
292
- };
293
-
294
- scrm_clockdomains: clockdomains {
295
- };
296
- };
297
-
298
- omap5_pmx_wkup: pinmux@c840 {
299
- compatible = "ti,omap5-padconf",
300
- "pinctrl-single";
301
- reg = <0xc840 0x003c>;
302
- #address-cells = <1>;
303
- #size-cells = <0>;
304
- #pinctrl-cells = <1>;
305
- #interrupt-cells = <1>;
306
- interrupt-controller;
307
- pinctrl-single,register-width = <16>;
308
- pinctrl-single,function-mask = <0x7fff>;
309
- };
310
-
311
- omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@cda0 {
312
- compatible = "ti,omap5-scm-wkup-pad-conf",
313
- "simple-bus";
314
- reg = <0xcda0 0x60>;
315
- #address-cells = <1>;
316
- #size-cells = <1>;
317
- ranges = <0 0xcda0 0x60>;
318
-
319
- scm_wkup_pad_conf: scm_conf@0 {
320
- compatible = "syscon", "simple-bus";
321
- reg = <0x0 0x60>;
322
- #address-cells = <1>;
323
- #size-cells = <1>;
324
- ranges = <0 0x0 0x60>;
325
-
326
- scm_wkup_pad_conf_clocks: clocks@0 {
327
- #address-cells = <1>;
328
- #size-cells = <0>;
329
- };
330
- };
331
- };
164
+ l4_cfg: interconnect@4a000000 {
332165 };
333166
334
- ocmcram: ocmcram@40300000 {
167
+ l4_per: interconnect@48000000 {
168
+ };
169
+
170
+ l4_abe: interconnect@40100000 {
171
+ };
172
+
173
+ ocmcram: sram@40300000 {
335174 compatible = "mmio-sram";
336175 reg = <0x40300000 0x20000>; /* 128k */
337
- };
338
-
339
- sdma: dma-controller@4a056000 {
340
- compatible = "ti,omap4430-sdma";
341
- reg = <0x4a056000 0x1000>;
342
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
343
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
344
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
345
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
346
- #dma-cells = <1>;
347
- dma-channels = <32>;
348
- dma-requests = <127>;
349
- ti,hwmods = "dma_system";
350
- };
351
-
352
- gpio1: gpio@4ae10000 {
353
- compatible = "ti,omap4-gpio";
354
- reg = <0x4ae10000 0x200>;
355
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
356
- ti,hwmods = "gpio1";
357
- ti,gpio-always-on;
358
- gpio-controller;
359
- #gpio-cells = <2>;
360
- interrupt-controller;
361
- #interrupt-cells = <2>;
362
- };
363
-
364
- gpio2: gpio@48055000 {
365
- compatible = "ti,omap4-gpio";
366
- reg = <0x48055000 0x200>;
367
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
368
- ti,hwmods = "gpio2";
369
- gpio-controller;
370
- #gpio-cells = <2>;
371
- interrupt-controller;
372
- #interrupt-cells = <2>;
373
- };
374
-
375
- gpio3: gpio@48057000 {
376
- compatible = "ti,omap4-gpio";
377
- reg = <0x48057000 0x200>;
378
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
379
- ti,hwmods = "gpio3";
380
- gpio-controller;
381
- #gpio-cells = <2>;
382
- interrupt-controller;
383
- #interrupt-cells = <2>;
384
- };
385
-
386
- gpio4: gpio@48059000 {
387
- compatible = "ti,omap4-gpio";
388
- reg = <0x48059000 0x200>;
389
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
390
- ti,hwmods = "gpio4";
391
- gpio-controller;
392
- #gpio-cells = <2>;
393
- interrupt-controller;
394
- #interrupt-cells = <2>;
395
- };
396
-
397
- gpio5: gpio@4805b000 {
398
- compatible = "ti,omap4-gpio";
399
- reg = <0x4805b000 0x200>;
400
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
401
- ti,hwmods = "gpio5";
402
- gpio-controller;
403
- #gpio-cells = <2>;
404
- interrupt-controller;
405
- #interrupt-cells = <2>;
406
- };
407
-
408
- gpio6: gpio@4805d000 {
409
- compatible = "ti,omap4-gpio";
410
- reg = <0x4805d000 0x200>;
411
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
412
- ti,hwmods = "gpio6";
413
- gpio-controller;
414
- #gpio-cells = <2>;
415
- interrupt-controller;
416
- #interrupt-cells = <2>;
417
- };
418
-
419
- gpio7: gpio@48051000 {
420
- compatible = "ti,omap4-gpio";
421
- reg = <0x48051000 0x200>;
422
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
423
- ti,hwmods = "gpio7";
424
- gpio-controller;
425
- #gpio-cells = <2>;
426
- interrupt-controller;
427
- #interrupt-cells = <2>;
428
- };
429
-
430
- gpio8: gpio@48053000 {
431
- compatible = "ti,omap4-gpio";
432
- reg = <0x48053000 0x200>;
433
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
434
- ti,hwmods = "gpio8";
435
- gpio-controller;
436
- #gpio-cells = <2>;
437
- interrupt-controller;
438
- #interrupt-cells = <2>;
439176 };
440177
441178 gpmc: gpmc@50000000 {
....@@ -457,427 +194,56 @@
457194 #gpio-cells = <2>;
458195 };
459196
460
- i2c1: i2c@48070000 {
461
- compatible = "ti,omap4-i2c";
462
- reg = <0x48070000 0x100>;
463
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
464
- #address-cells = <1>;
465
- #size-cells = <0>;
466
- ti,hwmods = "i2c1";
467
- };
468
-
469
- i2c2: i2c@48072000 {
470
- compatible = "ti,omap4-i2c";
471
- reg = <0x48072000 0x100>;
472
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
473
- #address-cells = <1>;
474
- #size-cells = <0>;
475
- ti,hwmods = "i2c2";
476
- };
477
-
478
- i2c3: i2c@48060000 {
479
- compatible = "ti,omap4-i2c";
480
- reg = <0x48060000 0x100>;
481
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
482
- #address-cells = <1>;
483
- #size-cells = <0>;
484
- ti,hwmods = "i2c3";
485
- };
486
-
487
- i2c4: i2c@4807a000 {
488
- compatible = "ti,omap4-i2c";
489
- reg = <0x4807a000 0x100>;
490
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
491
- #address-cells = <1>;
492
- #size-cells = <0>;
493
- ti,hwmods = "i2c4";
494
- };
495
-
496
- i2c5: i2c@4807c000 {
497
- compatible = "ti,omap4-i2c";
498
- reg = <0x4807c000 0x100>;
499
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
500
- #address-cells = <1>;
501
- #size-cells = <0>;
502
- ti,hwmods = "i2c5";
503
- };
504
-
505
- hwspinlock: spinlock@4a0f6000 {
506
- compatible = "ti,omap4-hwspinlock";
507
- reg = <0x4a0f6000 0x1000>;
508
- ti,hwmods = "spinlock";
509
- #hwlock-cells = <1>;
510
- };
511
-
512
- mcspi1: spi@48098000 {
513
- compatible = "ti,omap4-mcspi";
514
- reg = <0x48098000 0x200>;
515
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
516
- #address-cells = <1>;
517
- #size-cells = <0>;
518
- ti,hwmods = "mcspi1";
519
- ti,spi-num-cs = <4>;
520
- dmas = <&sdma 35>,
521
- <&sdma 36>,
522
- <&sdma 37>,
523
- <&sdma 38>,
524
- <&sdma 39>,
525
- <&sdma 40>,
526
- <&sdma 41>,
527
- <&sdma 42>;
528
- dma-names = "tx0", "rx0", "tx1", "rx1",
529
- "tx2", "rx2", "tx3", "rx3";
530
- };
531
-
532
- mcspi2: spi@4809a000 {
533
- compatible = "ti,omap4-mcspi";
534
- reg = <0x4809a000 0x200>;
535
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
536
- #address-cells = <1>;
537
- #size-cells = <0>;
538
- ti,hwmods = "mcspi2";
539
- ti,spi-num-cs = <2>;
540
- dmas = <&sdma 43>,
541
- <&sdma 44>,
542
- <&sdma 45>,
543
- <&sdma 46>;
544
- dma-names = "tx0", "rx0", "tx1", "rx1";
545
- };
546
-
547
- mcspi3: spi@480b8000 {
548
- compatible = "ti,omap4-mcspi";
549
- reg = <0x480b8000 0x200>;
550
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
551
- #address-cells = <1>;
552
- #size-cells = <0>;
553
- ti,hwmods = "mcspi3";
554
- ti,spi-num-cs = <2>;
555
- dmas = <&sdma 15>, <&sdma 16>;
556
- dma-names = "tx0", "rx0";
557
- };
558
-
559
- mcspi4: spi@480ba000 {
560
- compatible = "ti,omap4-mcspi";
561
- reg = <0x480ba000 0x200>;
562
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
563
- #address-cells = <1>;
564
- #size-cells = <0>;
565
- ti,hwmods = "mcspi4";
566
- ti,spi-num-cs = <1>;
567
- dmas = <&sdma 70>, <&sdma 71>;
568
- dma-names = "tx0", "rx0";
569
- };
570
-
571
- uart1: serial@4806a000 {
572
- compatible = "ti,omap4-uart";
573
- reg = <0x4806a000 0x100>;
574
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
575
- ti,hwmods = "uart1";
576
- clock-frequency = <48000000>;
577
- };
578
-
579
- uart2: serial@4806c000 {
580
- compatible = "ti,omap4-uart";
581
- reg = <0x4806c000 0x100>;
582
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
583
- ti,hwmods = "uart2";
584
- clock-frequency = <48000000>;
585
- };
586
-
587
- uart3: serial@48020000 {
588
- compatible = "ti,omap4-uart";
589
- reg = <0x48020000 0x100>;
590
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
591
- ti,hwmods = "uart3";
592
- clock-frequency = <48000000>;
593
- };
594
-
595
- uart4: serial@4806e000 {
596
- compatible = "ti,omap4-uart";
597
- reg = <0x4806e000 0x100>;
598
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
599
- ti,hwmods = "uart4";
600
- clock-frequency = <48000000>;
601
- };
602
-
603
- uart5: serial@48066000 {
604
- compatible = "ti,omap4-uart";
605
- reg = <0x48066000 0x100>;
606
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
607
- ti,hwmods = "uart5";
608
- clock-frequency = <48000000>;
609
- };
610
-
611
- uart6: serial@48068000 {
612
- compatible = "ti,omap4-uart";
613
- reg = <0x48068000 0x100>;
614
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
615
- ti,hwmods = "uart6";
616
- clock-frequency = <48000000>;
617
- };
618
-
619
- mmc1: mmc@4809c000 {
620
- compatible = "ti,omap4-hsmmc";
621
- reg = <0x4809c000 0x400>;
622
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
623
- ti,hwmods = "mmc1";
624
- ti,dual-volt;
625
- ti,needs-special-reset;
626
- dmas = <&sdma 61>, <&sdma 62>;
627
- dma-names = "tx", "rx";
628
- pbias-supply = <&pbias_mmc_reg>;
629
- };
630
-
631
- mmc2: mmc@480b4000 {
632
- compatible = "ti,omap4-hsmmc";
633
- reg = <0x480b4000 0x400>;
634
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
635
- ti,hwmods = "mmc2";
636
- ti,needs-special-reset;
637
- dmas = <&sdma 47>, <&sdma 48>;
638
- dma-names = "tx", "rx";
639
- };
640
-
641
- mmc3: mmc@480ad000 {
642
- compatible = "ti,omap4-hsmmc";
643
- reg = <0x480ad000 0x400>;
644
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
645
- ti,hwmods = "mmc3";
646
- ti,needs-special-reset;
647
- dmas = <&sdma 77>, <&sdma 78>;
648
- dma-names = "tx", "rx";
649
- };
650
-
651
- mmc4: mmc@480d1000 {
652
- compatible = "ti,omap4-hsmmc";
653
- reg = <0x480d1000 0x400>;
654
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
655
- ti,hwmods = "mmc4";
656
- ti,needs-special-reset;
657
- dmas = <&sdma 57>, <&sdma 58>;
658
- dma-names = "tx", "rx";
659
- };
660
-
661
- mmc5: mmc@480d5000 {
662
- compatible = "ti,omap4-hsmmc";
663
- reg = <0x480d5000 0x400>;
664
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
665
- ti,hwmods = "mmc5";
666
- ti,needs-special-reset;
667
- dmas = <&sdma 59>, <&sdma 60>;
668
- dma-names = "tx", "rx";
669
- };
670
-
671
- mmu_dsp: mmu@4a066000 {
672
- compatible = "ti,omap4-iommu";
673
- reg = <0x4a066000 0x100>;
674
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
675
- ti,hwmods = "mmu_dsp";
676
- #iommu-cells = <0>;
677
- };
678
-
679
- mmu_ipu: mmu@55082000 {
680
- compatible = "ti,omap4-iommu";
681
- reg = <0x55082000 0x100>;
682
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
683
- ti,hwmods = "mmu_ipu";
684
- #iommu-cells = <0>;
685
- ti,iommu-bus-err-back;
686
- };
687
-
688
- keypad: keypad@4ae1c000 {
689
- compatible = "ti,omap4-keypad";
690
- reg = <0x4ae1c000 0x400>;
691
- ti,hwmods = "kbd";
692
- };
693
-
694
- mcpdm: mcpdm@40132000 {
695
- compatible = "ti,omap4-mcpdm";
696
- reg = <0x40132000 0x7f>, /* MPU private access */
697
- <0x49032000 0x7f>; /* L3 Interconnect */
698
- reg-names = "mpu", "dma";
699
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
700
- ti,hwmods = "mcpdm";
701
- dmas = <&sdma 65>,
702
- <&sdma 66>;
703
- dma-names = "up_link", "dn_link";
704
- status = "disabled";
705
- };
706
-
707
- dmic: dmic@4012e000 {
708
- compatible = "ti,omap4-dmic";
709
- reg = <0x4012e000 0x7f>, /* MPU private access */
710
- <0x4902e000 0x7f>; /* L3 Interconnect */
711
- reg-names = "mpu", "dma";
712
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
713
- ti,hwmods = "dmic";
714
- dmas = <&sdma 67>;
715
- dma-names = "up_link";
716
- status = "disabled";
717
- };
718
-
719
- mcbsp1: mcbsp@40122000 {
720
- compatible = "ti,omap4-mcbsp";
721
- reg = <0x40122000 0xff>, /* MPU private access */
722
- <0x49022000 0xff>; /* L3 Interconnect */
723
- reg-names = "mpu", "dma";
724
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
725
- interrupt-names = "common";
726
- ti,buffer-size = <128>;
727
- ti,hwmods = "mcbsp1";
728
- dmas = <&sdma 33>,
729
- <&sdma 34>;
730
- dma-names = "tx", "rx";
731
- status = "disabled";
732
- };
733
-
734
- mcbsp2: mcbsp@40124000 {
735
- compatible = "ti,omap4-mcbsp";
736
- reg = <0x40124000 0xff>, /* MPU private access */
737
- <0x49024000 0xff>; /* L3 Interconnect */
738
- reg-names = "mpu", "dma";
739
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
740
- interrupt-names = "common";
741
- ti,buffer-size = <128>;
742
- ti,hwmods = "mcbsp2";
743
- dmas = <&sdma 17>,
744
- <&sdma 18>;
745
- dma-names = "tx", "rx";
746
- status = "disabled";
747
- };
748
-
749
- mcbsp3: mcbsp@40126000 {
750
- compatible = "ti,omap4-mcbsp";
751
- reg = <0x40126000 0xff>, /* MPU private access */
752
- <0x49026000 0xff>; /* L3 Interconnect */
753
- reg-names = "mpu", "dma";
754
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
755
- interrupt-names = "common";
756
- ti,buffer-size = <128>;
757
- ti,hwmods = "mcbsp3";
758
- dmas = <&sdma 19>,
759
- <&sdma 20>;
760
- dma-names = "tx", "rx";
761
- status = "disabled";
762
- };
763
-
764
- mailbox: mailbox@4a0f4000 {
765
- compatible = "ti,omap4-mailbox";
766
- reg = <0x4a0f4000 0x200>;
767
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
768
- ti,hwmods = "mailbox";
769
- #mbox-cells = <1>;
770
- ti,mbox-num-users = <3>;
771
- ti,mbox-num-fifos = <8>;
772
- mbox_ipu: mbox_ipu {
773
- ti,mbox-tx = <0 0 0>;
774
- ti,mbox-rx = <1 0 0>;
775
- };
776
- mbox_dsp: mbox_dsp {
777
- ti,mbox-tx = <3 0 0>;
778
- ti,mbox-rx = <2 0 0>;
779
- };
780
- };
781
-
782
- timer1: timer@4ae18000 {
783
- compatible = "ti,omap5430-timer";
784
- reg = <0x4ae18000 0x80>;
785
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
786
- ti,hwmods = "timer1";
787
- ti,timer-alwon;
788
- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
197
+ target-module@55082000 {
198
+ compatible = "ti,sysc-omap2", "ti,sysc";
199
+ reg = <0x55082000 0x4>,
200
+ <0x55082010 0x4>,
201
+ <0x55082014 0x4>;
202
+ reg-names = "rev", "sysc", "syss";
203
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
204
+ <SYSC_IDLE_NO>,
205
+ <SYSC_IDLE_SMART>;
206
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
207
+ SYSC_OMAP2_SOFTRESET |
208
+ SYSC_OMAP2_AUTOIDLE)>;
209
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
789210 clock-names = "fck";
211
+ resets = <&prm_core 2>;
212
+ reset-names = "rstctrl";
213
+ ranges = <0x0 0x55082000 0x100>;
214
+ #size-cells = <1>;
215
+ #address-cells = <1>;
216
+
217
+ mmu_ipu: mmu@0 {
218
+ compatible = "ti,omap4-iommu";
219
+ reg = <0x0 0x100>;
220
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
221
+ #iommu-cells = <0>;
222
+ ti,iommu-bus-err-back;
223
+ };
790224 };
791225
792
- timer2: timer@48032000 {
793
- compatible = "ti,omap5430-timer";
794
- reg = <0x48032000 0x80>;
795
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
796
- ti,hwmods = "timer2";
226
+ dsp: dsp {
227
+ compatible = "ti,omap5-dsp";
228
+ ti,bootreg = <&scm_conf 0x304 0>;
229
+ iommus = <&mmu_dsp>;
230
+ resets = <&prm_dsp 0>;
231
+ clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
232
+ firmware-name = "omap5-dsp-fw.xe64T";
233
+ mboxes = <&mailbox &mbox_dsp>;
234
+ status = "disabled";
797235 };
798236
799
- timer3: timer@48034000 {
800
- compatible = "ti,omap5430-timer";
801
- reg = <0x48034000 0x80>;
802
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
803
- ti,hwmods = "timer3";
804
- };
805
-
806
- timer4: timer@48036000 {
807
- compatible = "ti,omap5430-timer";
808
- reg = <0x48036000 0x80>;
809
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
810
- ti,hwmods = "timer4";
811
- };
812
-
813
- timer5: timer@40138000 {
814
- compatible = "ti,omap5430-timer";
815
- reg = <0x40138000 0x80>,
816
- <0x49038000 0x80>;
817
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
818
- ti,hwmods = "timer5";
819
- ti,timer-dsp;
820
- ti,timer-pwm;
821
- };
822
-
823
- timer6: timer@4013a000 {
824
- compatible = "ti,omap5430-timer";
825
- reg = <0x4013a000 0x80>,
826
- <0x4903a000 0x80>;
827
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
828
- ti,hwmods = "timer6";
829
- ti,timer-dsp;
830
- ti,timer-pwm;
831
- };
832
-
833
- timer7: timer@4013c000 {
834
- compatible = "ti,omap5430-timer";
835
- reg = <0x4013c000 0x80>,
836
- <0x4903c000 0x80>;
837
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
838
- ti,hwmods = "timer7";
839
- ti,timer-dsp;
840
- };
841
-
842
- timer8: timer@4013e000 {
843
- compatible = "ti,omap5430-timer";
844
- reg = <0x4013e000 0x80>,
845
- <0x4903e000 0x80>;
846
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
847
- ti,hwmods = "timer8";
848
- ti,timer-dsp;
849
- ti,timer-pwm;
850
- };
851
-
852
- timer9: timer@4803e000 {
853
- compatible = "ti,omap5430-timer";
854
- reg = <0x4803e000 0x80>;
855
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
856
- ti,hwmods = "timer9";
857
- ti,timer-pwm;
858
- };
859
-
860
- timer10: timer@48086000 {
861
- compatible = "ti,omap5430-timer";
862
- reg = <0x48086000 0x80>;
863
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
864
- ti,hwmods = "timer10";
865
- ti,timer-pwm;
866
- };
867
-
868
- timer11: timer@48088000 {
869
- compatible = "ti,omap5430-timer";
870
- reg = <0x48088000 0x80>;
871
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
872
- ti,hwmods = "timer11";
873
- ti,timer-pwm;
874
- };
875
-
876
- wdt2: wdt@4ae14000 {
877
- compatible = "ti,omap5-wdt", "ti,omap3-wdt";
878
- reg = <0x4ae14000 0x80>;
879
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
880
- ti,hwmods = "wd_timer2";
237
+ ipu: ipu@55020000 {
238
+ compatible = "ti,omap5-ipu";
239
+ reg = <0x55020000 0x10000>;
240
+ reg-names = "l2ram";
241
+ iommus = <&mmu_ipu>;
242
+ resets = <&prm_core 0>, <&prm_core 1>;
243
+ clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
244
+ firmware-name = "omap5-ipu-fw.xem4";
245
+ mboxes = <&mailbox &mbox_ipu>;
246
+ status = "disabled";
881247 };
882248
883249 dmm@4e000000 {
....@@ -911,96 +277,89 @@
911277 hw-caps-temp-alert;
912278 };
913279
914
- usb3: omap_dwc3@4a020000 {
915
- compatible = "ti,dwc3";
916
- ti,hwmods = "usb_otg_ss";
917
- reg = <0x4a020000 0x10000>;
918
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
280
+ aes1_target: target-module@4b501000 {
281
+ compatible = "ti,sysc-omap2", "ti,sysc";
282
+ reg = <0x4b501080 0x4>,
283
+ <0x4b501084 0x4>,
284
+ <0x4b501088 0x4>;
285
+ reg-names = "rev", "sysc", "syss";
286
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
287
+ SYSC_OMAP2_AUTOIDLE)>;
288
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
289
+ <SYSC_IDLE_NO>,
290
+ <SYSC_IDLE_SMART>,
291
+ <SYSC_IDLE_SMART_WKUP>;
292
+ ti,syss-mask = <1>;
293
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
294
+ clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
295
+ clock-names = "fck";
919296 #address-cells = <1>;
920297 #size-cells = <1>;
921
- utmi-mode = <2>;
922
- ranges;
923
- dwc3: dwc3@4a030000 {
924
- compatible = "snps,dwc3";
925
- reg = <0x4a030000 0x10000>;
926
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
927
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
928
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
929
- interrupt-names = "peripheral",
930
- "host",
931
- "otg";
932
- phys = <&usb2_phy>, <&usb3_phy>;
933
- phy-names = "usb2-phy", "usb3-phy";
934
- dr_mode = "peripheral";
298
+ ranges = <0x0 0x4b501000 0x1000>;
299
+
300
+ aes1: aes@0 {
301
+ compatible = "ti,omap4-aes";
302
+ reg = <0 0xa0>;
303
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
304
+ dmas = <&sdma 111>, <&sdma 110>;
305
+ dma-names = "tx", "rx";
935306 };
936307 };
937308
938
- ocp2scp@4a080000 {
939
- compatible = "ti,omap-ocp2scp";
309
+ aes2_target: target-module@4b701000 {
310
+ compatible = "ti,sysc-omap2", "ti,sysc";
311
+ reg = <0x4b701080 0x4>,
312
+ <0x4b701084 0x4>,
313
+ <0x4b701088 0x4>;
314
+ reg-names = "rev", "sysc", "syss";
315
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
316
+ SYSC_OMAP2_AUTOIDLE)>;
317
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
318
+ <SYSC_IDLE_NO>,
319
+ <SYSC_IDLE_SMART>,
320
+ <SYSC_IDLE_SMART_WKUP>;
321
+ ti,syss-mask = <1>;
322
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
323
+ clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
324
+ clock-names = "fck";
940325 #address-cells = <1>;
941326 #size-cells = <1>;
942
- reg = <0x4a080000 0x20>;
943
- ranges;
944
- ti,hwmods = "ocp2scp1";
945
- usb2_phy: usb2phy@4a084000 {
946
- compatible = "ti,omap-usb2";
947
- reg = <0x4a084000 0x7c>;
948
- syscon-phy-power = <&scm_conf 0x300>;
949
- clocks = <&usb_phy_cm_clk32k>,
950
- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
951
- clock-names = "wkupclk", "refclk";
952
- #phy-cells = <0>;
953
- };
327
+ ranges = <0x0 0x4b701000 0x1000>;
954328
955
- usb3_phy: usb3phy@4a084400 {
956
- compatible = "ti,omap-usb3";
957
- reg = <0x4a084400 0x80>,
958
- <0x4a084800 0x64>,
959
- <0x4a084c00 0x40>;
960
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
961
- syscon-phy-power = <&scm_conf 0x370>;
962
- clocks = <&usb_phy_cm_clk32k>,
963
- <&sys_clkin>,
964
- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
965
- clock-names = "wkupclk",
966
- "sysclk",
967
- "refclk";
968
- #phy-cells = <0>;
329
+ aes2: aes@0 {
330
+ compatible = "ti,omap4-aes";
331
+ reg = <0 0xa0>;
332
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
333
+ dmas = <&sdma 114>, <&sdma 113>;
334
+ dma-names = "tx", "rx";
969335 };
970336 };
971337
972
- usbhstll: usbhstll@4a062000 {
973
- compatible = "ti,usbhs-tll";
974
- reg = <0x4a062000 0x1000>;
975
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
976
- ti,hwmods = "usb_tll_hs";
977
- };
978
-
979
- usbhshost: usbhshost@4a064000 {
980
- compatible = "ti,usbhs-host";
981
- reg = <0x4a064000 0x800>;
982
- ti,hwmods = "usb_host_hs";
338
+ sham_target: target-module@4b100000 {
339
+ compatible = "ti,sysc-omap3-sham", "ti,sysc";
340
+ reg = <0x4b100100 0x4>,
341
+ <0x4b100110 0x4>,
342
+ <0x4b100114 0x4>;
343
+ reg-names = "rev", "sysc", "syss";
344
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
345
+ SYSC_OMAP2_AUTOIDLE)>;
346
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
347
+ <SYSC_IDLE_NO>,
348
+ <SYSC_IDLE_SMART>;
349
+ ti,syss-mask = <1>;
350
+ /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
351
+ clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
352
+ clock-names = "fck";
983353 #address-cells = <1>;
984354 #size-cells = <1>;
985
- ranges;
986
- clocks = <&l3init_60m_fclk>,
987
- <&xclk60mhsp1_ck>,
988
- <&xclk60mhsp2_ck>;
989
- clock-names = "refclk_60m_int",
990
- "refclk_60m_ext_p1",
991
- "refclk_60m_ext_p2";
355
+ ranges = <0x0 0x4b100000 0x1000>;
992356
993
- usbhsohci: ohci@4a064800 {
994
- compatible = "ti,ohci-omap3";
995
- reg = <0x4a064800 0x400>;
996
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
997
- remote-wakeup-connected;
998
- };
999
-
1000
- usbhsehci: ehci@4a064c00 {
1001
- compatible = "ti,ehci-omap";
1002
- reg = <0x4a064c00 0x400>;
1003
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
357
+ sham: sham@0 {
358
+ compatible = "ti,omap4-sham";
359
+ reg = <0 0x300>;
360
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
361
+ dmas = <&sdma 119>;
362
+ dma-names = "rx";
1004363 };
1005364 };
1006365
....@@ -1016,27 +375,6 @@
1016375 };
1017376
1018377 /* OCP2SCP3 */
1019
- ocp2scp@4a090000 {
1020
- compatible = "ti,omap-ocp2scp";
1021
- #address-cells = <1>;
1022
- #size-cells = <1>;
1023
- reg = <0x4a090000 0x20>;
1024
- ranges;
1025
- ti,hwmods = "ocp2scp3";
1026
- sata_phy: phy@4a096000 {
1027
- compatible = "ti,phy-pipe3-sata";
1028
- reg = <0x4A096000 0x80>, /* phy_rx */
1029
- <0x4A096400 0x64>, /* phy_tx */
1030
- <0x4A096800 0x40>; /* pll_ctrl */
1031
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1032
- syscon-phy-power = <&scm_conf 0x374>;
1033
- clocks = <&sys_clkin>,
1034
- <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
1035
- clock-names = "sysclk", "refclk";
1036
- #phy-cells = <0>;
1037
- };
1038
- };
1039
-
1040378 sata: sata@4a141100 {
1041379 compatible = "snps,dwc-ahci";
1042380 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
....@@ -1048,78 +386,210 @@
1048386 ports-implemented = <0x1>;
1049387 };
1050388
1051
- dss: dss@58000000 {
1052
- compatible = "ti,omap5-dss";
1053
- reg = <0x58000000 0x80>;
1054
- status = "disabled";
1055
- ti,hwmods = "dss_core";
1056
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
389
+ target-module@56000000 {
390
+ compatible = "ti,sysc-omap4", "ti,sysc";
391
+ reg = <0x5600fe00 0x4>,
392
+ <0x5600fe10 0x4>;
393
+ reg-names = "rev", "sysc";
394
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
395
+ <SYSC_IDLE_NO>,
396
+ <SYSC_IDLE_SMART>;
397
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
398
+ <SYSC_IDLE_NO>,
399
+ <SYSC_IDLE_SMART>;
400
+ clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
1057401 clock-names = "fck";
1058402 #address-cells = <1>;
1059403 #size-cells = <1>;
1060
- ranges;
404
+ ranges = <0 0x56000000 0x2000000>;
1061405
1062
- dispc@58001000 {
1063
- compatible = "ti,omap5-dispc";
1064
- reg = <0x58001000 0x1000>;
1065
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1066
- ti,hwmods = "dss_dispc";
406
+ /*
407
+ * Closed source PowerVR driver, no child device
408
+ * binding or driver in mainline
409
+ */
410
+ };
411
+
412
+ target-module@58000000 {
413
+ compatible = "ti,sysc-omap2", "ti,sysc";
414
+ reg = <0x58000000 4>,
415
+ <0x58000014 4>;
416
+ reg-names = "rev", "syss";
417
+ ti,syss-mask = <1>;
418
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
419
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
420
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
421
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
422
+ clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
423
+ #address-cells = <1>;
424
+ #size-cells = <1>;
425
+ ranges = <0 0x58000000 0x1000000>;
426
+
427
+ dss: dss@0 {
428
+ compatible = "ti,omap5-dss";
429
+ reg = <0 0x80>;
430
+ status = "disabled";
1067431 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
1068432 clock-names = "fck";
1069
- };
433
+ #address-cells = <1>;
434
+ #size-cells = <1>;
435
+ ranges = <0 0 0x1000000>;
1070436
1071
- rfbi: encoder@58002000 {
1072
- compatible = "ti,omap5-rfbi";
1073
- reg = <0x58002000 0x100>;
1074
- status = "disabled";
1075
- ti,hwmods = "dss_rfbi";
1076
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
1077
- clock-names = "fck", "ick";
1078
- };
437
+ target-module@1000 {
438
+ compatible = "ti,sysc-omap2", "ti,sysc";
439
+ reg = <0x1000 0x4>,
440
+ <0x1010 0x4>,
441
+ <0x1014 0x4>;
442
+ reg-names = "rev", "sysc", "syss";
443
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
444
+ <SYSC_IDLE_NO>,
445
+ <SYSC_IDLE_SMART>;
446
+ ti,sysc-midle = <SYSC_IDLE_FORCE>,
447
+ <SYSC_IDLE_NO>,
448
+ <SYSC_IDLE_SMART>;
449
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
450
+ SYSC_OMAP2_ENAWAKEUP |
451
+ SYSC_OMAP2_SOFTRESET |
452
+ SYSC_OMAP2_AUTOIDLE)>;
453
+ ti,syss-mask = <1>;
454
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
455
+ clock-names = "fck";
456
+ #address-cells = <1>;
457
+ #size-cells = <1>;
458
+ ranges = <0 0x1000 0x1000>;
1079459
1080
- dsi1: encoder@58004000 {
1081
- compatible = "ti,omap5-dsi";
1082
- reg = <0x58004000 0x200>,
1083
- <0x58004200 0x40>,
1084
- <0x58004300 0x40>;
1085
- reg-names = "proto", "phy", "pll";
1086
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1087
- status = "disabled";
1088
- ti,hwmods = "dss_dsi1";
1089
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1090
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1091
- clock-names = "fck", "sys_clk";
1092
- };
460
+ dispc@0 {
461
+ compatible = "ti,omap5-dispc";
462
+ reg = <0 0x1000>;
463
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
464
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
465
+ clock-names = "fck";
466
+ };
467
+ };
1093468
1094
- dsi2: encoder@58005000 {
1095
- compatible = "ti,omap5-dsi";
1096
- reg = <0x58009000 0x200>,
1097
- <0x58009200 0x40>,
1098
- <0x58009300 0x40>;
1099
- reg-names = "proto", "phy", "pll";
1100
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1101
- status = "disabled";
1102
- ti,hwmods = "dss_dsi2";
1103
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
1104
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1105
- clock-names = "fck", "sys_clk";
1106
- };
469
+ target-module@2000 {
470
+ compatible = "ti,sysc-omap2", "ti,sysc";
471
+ reg = <0x2000 0x4>,
472
+ <0x2010 0x4>,
473
+ <0x2014 0x4>;
474
+ reg-names = "rev", "sysc", "syss";
475
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
476
+ <SYSC_IDLE_NO>,
477
+ <SYSC_IDLE_SMART>;
478
+ ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
479
+ SYSC_OMAP2_AUTOIDLE)>;
480
+ ti,syss-mask = <1>;
481
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
482
+ clock-names = "fck";
483
+ #address-cells = <1>;
484
+ #size-cells = <1>;
485
+ ranges = <0 0x2000 0x1000>;
1107486
1108
- hdmi: encoder@58060000 {
1109
- compatible = "ti,omap5-hdmi";
1110
- reg = <0x58040000 0x200>,
1111
- <0x58040200 0x80>,
1112
- <0x58040300 0x80>,
1113
- <0x58060000 0x19000>;
1114
- reg-names = "wp", "pll", "phy", "core";
1115
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1116
- status = "disabled";
1117
- ti,hwmods = "dss_hdmi";
1118
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
1119
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
1120
- clock-names = "fck", "sys_clk";
1121
- dmas = <&sdma 76>;
1122
- dma-names = "audio_tx";
487
+ rfbi: encoder@0 {
488
+ compatible = "ti,omap5-rfbi";
489
+ reg = <0 0x100>;
490
+ status = "disabled";
491
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
492
+ clock-names = "fck", "ick";
493
+ };
494
+ };
495
+
496
+ target-module@4000 {
497
+ compatible = "ti,sysc-omap2", "ti,sysc";
498
+ reg = <0x4000 0x4>,
499
+ <0x4010 0x4>,
500
+ <0x4014 0x4>;
501
+ reg-names = "rev", "sysc", "syss";
502
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
503
+ <SYSC_IDLE_NO>,
504
+ <SYSC_IDLE_SMART>;
505
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
506
+ SYSC_OMAP2_ENAWAKEUP |
507
+ SYSC_OMAP2_SOFTRESET |
508
+ SYSC_OMAP2_AUTOIDLE)>;
509
+ ti,syss-mask = <1>;
510
+ #address-cells = <1>;
511
+ #size-cells = <1>;
512
+ ranges = <0 0x4000 0x1000>;
513
+
514
+ dsi1: encoder@0 {
515
+ compatible = "ti,omap5-dsi";
516
+ reg = <0 0x200>,
517
+ <0x200 0x40>,
518
+ <0x300 0x40>;
519
+ reg-names = "proto", "phy", "pll";
520
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
521
+ status = "disabled";
522
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
523
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
524
+ clock-names = "fck", "sys_clk";
525
+ };
526
+ };
527
+
528
+ target-module@9000 {
529
+ compatible = "ti,sysc-omap2", "ti,sysc";
530
+ reg = <0x9000 0x4>,
531
+ <0x9010 0x4>,
532
+ <0x9014 0x4>;
533
+ reg-names = "rev", "sysc", "syss";
534
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
535
+ <SYSC_IDLE_NO>,
536
+ <SYSC_IDLE_SMART>;
537
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
538
+ SYSC_OMAP2_ENAWAKEUP |
539
+ SYSC_OMAP2_SOFTRESET |
540
+ SYSC_OMAP2_AUTOIDLE)>;
541
+ ti,syss-mask = <1>;
542
+ #address-cells = <1>;
543
+ #size-cells = <1>;
544
+ ranges = <0 0x9000 0x1000>;
545
+
546
+ dsi2: encoder@0 {
547
+ compatible = "ti,omap5-dsi";
548
+ reg = <0 0x200>,
549
+ <0x200 0x40>,
550
+ <0x300 0x40>;
551
+ reg-names = "proto", "phy", "pll";
552
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
553
+ status = "disabled";
554
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
555
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
556
+ clock-names = "fck", "sys_clk";
557
+ };
558
+ };
559
+
560
+ target-module@40000 {
561
+ compatible = "ti,sysc-omap4", "ti,sysc";
562
+ reg = <0x40000 0x4>,
563
+ <0x40010 0x4>;
564
+ reg-names = "rev", "sysc";
565
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
566
+ <SYSC_IDLE_NO>,
567
+ <SYSC_IDLE_SMART>,
568
+ <SYSC_IDLE_SMART_WKUP>;
569
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
570
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
571
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
572
+ clock-names = "fck", "dss_clk";
573
+ #address-cells = <1>;
574
+ #size-cells = <1>;
575
+ ranges = <0 0x40000 0x40000>;
576
+
577
+ hdmi: encoder@0 {
578
+ compatible = "ti,omap5-hdmi";
579
+ reg = <0 0x200>,
580
+ <0x200 0x80>,
581
+ <0x300 0x80>,
582
+ <0x20000 0x19000>;
583
+ reg-names = "wp", "pll", "phy", "core";
584
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
585
+ status = "disabled";
586
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
587
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
588
+ clock-names = "fck", "sys_clk";
589
+ dmas = <&sdma 76>;
590
+ dma-names = "audio_tx";
591
+ };
592
+ };
1123593 };
1124594 };
1125595
....@@ -1190,6 +660,7 @@
1190660 coefficients = <65 (-1791)>;
1191661 };
1192662
663
+#include "omap5-l4.dtsi"
1193664 #include "omap54xx-clocks.dtsi"
1194665
1195666 &gpu_thermal {
....@@ -1199,3 +670,48 @@
1199670 &core_thermal {
1200671 coefficients = <0 2000>;
1201672 };
673
+
674
+#include "omap5-l4-abe.dtsi"
675
+#include "omap54xx-clocks.dtsi"
676
+
677
+&prm {
678
+ prm_dsp: prm@400 {
679
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
680
+ reg = <0x400 0x100>;
681
+ #reset-cells = <1>;
682
+ };
683
+
684
+ prm_abe: prm@500 {
685
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
686
+ reg = <0x500 0x100>;
687
+ #power-domain-cells = <0>;
688
+ };
689
+
690
+ prm_core: prm@700 {
691
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
692
+ reg = <0x700 0x100>;
693
+ #reset-cells = <1>;
694
+ };
695
+
696
+ prm_iva: prm@1200 {
697
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
698
+ reg = <0x1200 0x100>;
699
+ #reset-cells = <1>;
700
+ };
701
+
702
+ prm_device: prm@1c00 {
703
+ compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
704
+ reg = <0x1c00 0x100>;
705
+ #reset-cells = <1>;
706
+ };
707
+};
708
+
709
+/* Preferred always-on timer for clockevent */
710
+&timer1_target {
711
+ ti,no-reset-on-init;
712
+ ti,no-idle;
713
+ timer@0 {
714
+ assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
715
+ assigned-clock-parents = <&sys_32k_ck>;
716
+ };
717
+};