add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/nspire.dtsi
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@@ -1,17 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  *  linux/arch/arm/boot/nspire.dtsi
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  *
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  *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2, as
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- * published by the Free Software Foundation.
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- *
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  */
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-/include/ "skeleton.dtsi"
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-
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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 	interrupt-parent = <&intc>;
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 	cpus {
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@@ -99,8 +95,14 @@
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 			reg = <0xC0000000 0x1000>;
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 			interrupts = <21>;
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-			clocks = <&apb_pclk>;
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-			clock-names = "apb_pclk";
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+			/*
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+			 * We assume the same clock is fed to APB and CLCDCLK.
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+			 * There is some code to scale the clock down by a factor
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+			 * 48 for the display so likely the frequency to the
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+			 * display is 1MHz and the CLCDCLK is 48 MHz.
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+			 */
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+			clocks = <&apb_pclk>, <&apb_pclk>;
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+			clock-names = "clcdclk", "apb_pclk";
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 		};
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 		adc: adc@C4000000 {
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@@ -143,15 +145,19 @@
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 			timer0: timer@900C0000 {
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 				reg = <0x900C0000 0x1000>;
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-
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-				clocks = <&timer_clk>;
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+				clocks = <&timer_clk>, <&timer_clk>,
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+					 <&timer_clk>;
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+				clock-names = "timer0clk", "timer1clk",
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+					      "apb_pclk";
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 			};
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 			timer1: timer@900D0000 {
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 				reg = <0x900D0000 0x1000>;
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 				interrupts = <19>;
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-
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-				clocks = <&timer_clk>;
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+				clocks = <&timer_clk>, <&timer_clk>,
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+					 <&timer_clk>;
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+				clock-names = "timer0clk", "timer1clk",
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+					      "apb_pclk";
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 			};
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 			watchdog: watchdog@90060000 {