add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/mmp2.dtsi
..
..
@@ -1,16 +1,16 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  *  Copyright (C) 2012 Marvell Technology Group Ltd.
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  *  Author: Haojian Zhuang <haojian.zhuang@marvell.com>
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- *
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- *  This program is free software; you can redistribute it and/or modify
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- *  it under the terms of the GNU General Public License version 2 as
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- *  publishhed by the Free Software Foundation.
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  */
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-#include "skeleton.dtsi"
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7
 #include <dt-bindings/clock/marvell,mmp2.h>
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+#include <dt-bindings/power/marvell,mmp2.h>
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9
 
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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+
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 	aliases {
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 		serial0 = &uart1;
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 		serial1 = &uart2;
..
..
@@ -38,6 +38,17 @@
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 			#size-cells = <1>;
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 			reg = <0xd4200000 0x00200000>;
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 			ranges;
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+
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+			gpu: gpu@d420d000 {
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+				compatible = "vivante,gc";
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+				reg = <0xd420d000 0x4000>;
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+				interrupts = <8>;
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+				status = "disabled";
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+				clocks = <&soc_clocks MMP2_CLK_GPU_3D>,
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+					 <&soc_clocks MMP2_CLK_GPU_BUS>;
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+				clock-names = "core", "bus";
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+				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
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+			};
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52
 
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 			intc: interrupt-controller@d4282000 {
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 				compatible = "mrvl,mmp2-intc";
..
..
@@ -117,6 +128,139 @@
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 				reg-names = "mux status", "mux mask";
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 				mrvl,intc-nr-irqs = <2>;
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 			};
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+
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+			usb_phy0: usb-phy@d4207000 {
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+				compatible = "marvell,mmp2-usb-phy";
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+				reg = <0xd4207000 0x40>;
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+				#phy-cells = <0>;
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+				status = "disabled";
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+			};
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+
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+			usb_otg0: usb-otg@d4208000 {
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+				compatible = "marvell,pxau2o-ehci";
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+				reg = <0xd4208000 0x200>;
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+				interrupts = <44>;
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+				clocks = <&soc_clocks MMP2_CLK_USB>;
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+				clock-names = "USBCLK";
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+				phys = <&usb_phy0>;
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+				phy-names = "usb";
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+				status = "disabled";
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+			};
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+
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+			mmc1: mmc@d4280000 {
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+				compatible = "mrvl,pxav3-mmc";
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+				reg = <0xd4280000 0x120>;
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+				clocks = <&soc_clocks MMP2_CLK_SDH0>;
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+				clock-names = "io";
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+				interrupts = <39>;
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+				status = "disabled";
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+			};
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+
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+			mmc2: mmc@d4280800 {
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+				compatible = "mrvl,pxav3-mmc";
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+				reg = <0xd4280800 0x120>;
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+				clocks = <&soc_clocks MMP2_CLK_SDH1>;
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+				clock-names = "io";
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+				interrupts = <52>;
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+				status = "disabled";
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+			};
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+
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+			mmc3: mmc@d4281000 {
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+				compatible = "mrvl,pxav3-mmc";
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+				reg = <0xd4281000 0x120>;
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+				clocks = <&soc_clocks MMP2_CLK_SDH2>;
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+				clock-names = "io";
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+				interrupts = <53>;
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+				status = "disabled";
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+			};
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+
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+			mmc4: mmc@d4281800 {
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+				compatible = "mrvl,pxav3-mmc";
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+				reg = <0xd4281800 0x120>;
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+				clocks = <&soc_clocks MMP2_CLK_SDH3>;
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+				clock-names = "io";
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+				interrupts = <54>;
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+				status = "disabled";
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+			};
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+
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+			camera0: camera@d420a000 {
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+				compatible = "marvell,mmp2-ccic";
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+				reg = <0xd420a000 0x800>;
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+				interrupts = <42>;
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+				clocks = <&soc_clocks MMP2_CLK_CCIC0>;
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+				clock-names = "axi";
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+				#clock-cells = <0>;
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+				clock-output-names = "mclk";
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+				status = "disabled";
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+			};
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+
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+			camera1: camera@d420a800 {
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+				compatible = "marvell,mmp2-ccic";
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+				reg = <0xd420a800 0x800>;
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+				interrupts = <30>;
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+				clocks = <&soc_clocks MMP2_CLK_CCIC1>;
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+				clock-names = "axi";
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+				#clock-cells = <0>;
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+				clock-output-names = "mclk";
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+				status = "disabled";
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+			};
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+
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+			adma0: dma-controller@d42a0800 {
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+				compatible = "marvell,adma-1.0";
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+				reg = <0xd42a0800 0x100>;
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+				interrupts = <48>;
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+				#dma-cells = <1>;
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+				asram = <&asram>;
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+				iram = <&asram>;
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+				status = "disabled";
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+			};
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+
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+			adma1: dma-controller@d42a0900 {
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+				compatible = "marvell,adma-1.0";
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+				reg = <0xd42a0900 0x100>;
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+				interrupts = <48>;
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+				#dma-cells = <1>;
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+				status = "disabled";
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+			};
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+
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+			audio_clk: clocks@d42a0c30 {
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+				compatible = "marvell,mmp2-audio-clock";
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+				reg = <0xd42a0c30 0x10>;
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+				clock-names = "audio", "vctcxo", "i2s0", "i2s1";
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+				clocks = <&soc_clocks MMP2_CLK_AUDIO>,
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+					 <&soc_clocks MMP2_CLK_VCTCXO>,
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+					 <&soc_clocks MMP2_CLK_I2S0>,
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+					 <&soc_clocks MMP2_CLK_I2S1>;
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+				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
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+				#clock-cells = <1>;
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+				status = "disabled";
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+			};
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+
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+			sspa0: audio-controller@d42a0c00 {
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+				compatible = "marvell,mmp-sspa";
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+				reg = <0xd42a0c00 0x30>,
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+				      <0xd42a0c80 0x30>;
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+				interrupts = <2>;
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+				clock-names = "audio", "bitclk";
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+				clocks = <&soc_clocks MMP2_CLK_AUDIO>,
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+					 <&audio_clk 1>;
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+				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
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+				#sound-dai-cells = <0>;
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+				status = "disabled";
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+			};
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+
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+			sspa1: audio-controller@d42a0d00 {
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+				compatible = "marvell,mmp-sspa";
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+				reg = <0xd42a0d00 0x30>,
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+				      <0xd42a0d80 0x30>;
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+				interrupts = <3>;
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+				clock-names = "audio", "bitclk";
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+				clocks = <&soc_clocks MMP2_CLK_AUDIO>,
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+					 <&audio_clk 2>;
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+				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_AUDIO>;
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+				#sound-dai-cells = <0>;
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+				status = "disabled";
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+			};
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 		};
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265
 
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 		apb@d4000000 {	/* APB */
..
..
@@ -126,49 +270,62 @@
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 			reg = <0xd4000000 0x00200000>;
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 			ranges;
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+			dma-controller@d4000000 {
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+				compatible = "marvell,pdma-1.0";
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+				reg = <0xd4000000 0x10000>;
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+				interrupts = <48>;
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+				#dma-channels = <16>;
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+				status = "disabled";
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+			};
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+
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 			timer0: timer@d4014000 {
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 				compatible = "mrvl,mmp-timer";
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 				reg = <0xd4014000 0x100>;
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 				interrupts = <13>;
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+				clocks = <&soc_clocks MMP2_CLK_TIMER>;
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 			};
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-			uart1: uart@d4030000 {
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-				compatible = "mrvl,mmp-uart";
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+			uart1: serial@d4030000 {
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+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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 				reg = <0xd4030000 0x1000>;
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 				interrupts = <27>;
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 				clocks = <&soc_clocks MMP2_CLK_UART0>;
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 				resets = <&soc_clocks MMP2_CLK_UART0>;
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+				reg-shift = <2>;
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 				status = "disabled";
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 			};
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-			uart2: uart@d4017000 {
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-				compatible = "mrvl,mmp-uart";
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+			uart2: serial@d4017000 {
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+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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 				reg = <0xd4017000 0x1000>;
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 				interrupts = <28>;
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 				clocks = <&soc_clocks MMP2_CLK_UART1>;
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 				resets = <&soc_clocks MMP2_CLK_UART1>;
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+				reg-shift = <2>;
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 				status = "disabled";
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 			};
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-			uart3: uart@d4018000 {
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-				compatible = "mrvl,mmp-uart";
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+			uart3: serial@d4018000 {
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+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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 				reg = <0xd4018000 0x1000>;
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 				interrupts = <24>;
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 				clocks = <&soc_clocks MMP2_CLK_UART2>;
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 				resets = <&soc_clocks MMP2_CLK_UART2>;
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+				reg-shift = <2>;
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 				status = "disabled";
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 			};
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-			uart4: uart@d4016000 {
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-				compatible = "mrvl,mmp-uart";
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+			uart4: serial@d4016000 {
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+				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
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 				reg = <0xd4016000 0x1000>;
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 				interrupts = <46>;
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 				clocks = <&soc_clocks MMP2_CLK_UART3>;
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 				resets = <&soc_clocks MMP2_CLK_UART3>;
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+				reg-shift = <2>;
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 				status = "disabled";
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 			};
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-			gpio@d4019000 {
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+			gpio: gpio@d4019000 {
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 				compatible = "marvell,mmp2-gpio";
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 				#address-cells = <1>;
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 				#size-cells = <1>;
..
..
@@ -232,26 +389,125 @@
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 				status = "disabled";
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 			};
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+			twsi3: i2c@d4032000 {
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+				compatible = "mrvl,mmp-twsi";
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+				reg = <0xd4032000 0x1000>;
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+				interrupt-parent = <&intcmux17>;
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+				interrupts = <1>;
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+				clocks = <&soc_clocks MMP2_CLK_TWSI2>;
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+				resets = <&soc_clocks MMP2_CLK_TWSI2>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				status = "disabled";
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+			};
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+
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+			twsi4: i2c@d4033000 {
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+				compatible = "mrvl,mmp-twsi";
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+				reg = <0xd4033000 0x1000>;
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+				interrupt-parent = <&intcmux17>;
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+				interrupts = <2>;
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+				clocks = <&soc_clocks MMP2_CLK_TWSI3>;
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+				resets = <&soc_clocks MMP2_CLK_TWSI3>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				status = "disabled";
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+			};
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+
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+
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+			twsi5: i2c@d4033800 {
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+				compatible = "mrvl,mmp-twsi";
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+				reg = <0xd4033800 0x1000>;
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+				interrupt-parent = <&intcmux17>;
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+				interrupts = <3>;
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+				clocks = <&soc_clocks MMP2_CLK_TWSI4>;
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+				resets = <&soc_clocks MMP2_CLK_TWSI4>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				status = "disabled";
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+			};
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+
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+			twsi6: i2c@d4034000 {
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+				compatible = "mrvl,mmp-twsi";
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+				reg = <0xd4034000 0x1000>;
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+				interrupt-parent = <&intcmux17>;
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+				interrupts = <4>;
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+				clocks = <&soc_clocks MMP2_CLK_TWSI5>;
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+				resets = <&soc_clocks MMP2_CLK_TWSI5>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				status = "disabled";
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+			};
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+
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 			rtc: rtc@d4010000 {
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 				compatible = "mrvl,mmp-rtc";
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 				reg = <0xd4010000 0x1000>;
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-				interrupts = <1 0>;
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+				interrupts = <1>, <0>;
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 				interrupt-names = "rtc 1Hz", "rtc alarm";
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 				interrupt-parent = <&intcmux5>;
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 				clocks = <&soc_clocks MMP2_CLK_RTC>;
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 				resets = <&soc_clocks MMP2_CLK_RTC>;
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 				status = "disabled";
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 			};
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+
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+			ssp1: spi@d4035000 {
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+				compatible = "marvell,mmp2-ssp";
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+				reg = <0xd4035000 0x1000>;
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+				clocks = <&soc_clocks MMP2_CLK_SSP0>;
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+				interrupts = <0>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				status = "disabled";
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+			};
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+
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+			ssp2: spi@d4036000 {
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+				compatible = "marvell,mmp2-ssp";
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+				reg = <0xd4036000 0x1000>;
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+				clocks = <&soc_clocks MMP2_CLK_SSP1>;
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+				interrupts = <1>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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+				status = "disabled";
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+			};
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+
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+			ssp3: spi@d4037000 {
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+				compatible = "marvell,mmp2-ssp";
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+				reg = <0xd4037000 0x1000>;
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+				clocks = <&soc_clocks MMP2_CLK_SSP2>;
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+				interrupts = <20>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
479
+				status = "disabled";
480
+			};
481
+
482
+			ssp4: spi@d4039000 {
483
+				compatible = "marvell,mmp2-ssp";
484
+				reg = <0xd4039000 0x1000>;
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+				clocks = <&soc_clocks MMP2_CLK_SSP3>;
486
+				interrupts = <21>;
487
+				#address-cells = <1>;
488
+				#size-cells = <0>;
489
+				status = "disabled";
490
+			};
245
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 		};
246
492
 
247
-		soc_clocks: clocks{
493
+		asram: sram@e0000000 {
494
+			compatible = "mmio-sram";
495
+			reg = <0xe0000000 0x10000>;
496
+			ranges = <0 0xe0000000 0x10000>;
497
+			#address-cells = <1>;
498
+			#size-cells = <1>;
499
+			status = "disabled";
500
+		};
501
+
502
+		soc_clocks: clocks {
248
503
 			compatible = "marvell,mmp2-clock";
249
-			reg = <0xd4050000 0x1000>,
504
+			reg = <0xd4050000 0x2000>,
250
505
 			      <0xd4282800 0x400>,
251
506
 			      <0xd4015000 0x1000>;
252
507
 			reg-names = "mpmu", "apmu", "apbc";
253
508
 			#clock-cells = <1>;
254
509
 			#reset-cells = <1>;
510
+			#power-domain-cells = <1>;
255
511
 		};
256
512
 	};
257
513
 };