add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/lpc32xx.dtsi
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@@ -1,22 +1,17 @@
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+// SPDX-License-Identifier: GPL-2.0+
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 /*
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  * NXP LPC32xx SoC
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  *
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+ * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
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  * Copyright 2012 Roland Stigge <stigge@antcom.de>
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- *
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- * The code contained herein is licensed under the GNU General Public
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- * License. You may obtain a copy of the GNU General Public License
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- * Version 2 or later at the following locations:
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- *
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- * http://www.opensource.org/licenses/gpl-license.html
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- * http://www.gnu.org/copyleft/gpl.html
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  */
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-
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-#include "skeleton.dtsi"
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8
 
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 #include <dt-bindings/clock/lpc32xx-clock.h>
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 #include <dt-bindings/interrupt-controller/irq.h>
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 / {
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+	#address-cells = <1>;
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+	#size-cells = <1>;
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 	compatible = "nxp,lpc3220";
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 	interrupt-parent = <&mic>;
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@@ -152,6 +147,7 @@
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 			reg = <0x31060000 0x1000>;
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 			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
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 			clocks = <&clk LPC32XX_CLK_MAC>;
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+			status = "disabled";
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 		};
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 		emc: memory-controller@31080000 {
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@@ -185,6 +181,8 @@
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 				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
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 				clocks = <&clk LPC32XX_CLK_SSP0>;
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 				clock-names = "apb_pclk";
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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 				status = "disabled";
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 			};
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@@ -192,6 +190,8 @@
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 				compatible = "nxp,lpc3220-spi";
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 				reg = <0x20088000 0x1000>;
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 				clocks = <&clk LPC32XX_CLK_SPI1>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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 				status = "disabled";
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 			};
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@@ -205,6 +205,8 @@
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 				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
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 				clocks = <&clk LPC32XX_CLK_SSP1>;
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 				clock-names = "apb_pclk";
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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 				status = "disabled";
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 			};
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@@ -212,12 +214,15 @@
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 				compatible = "nxp,lpc3220-spi";
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 				reg = <0x20090000 0x1000>;
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 				clocks = <&clk LPC32XX_CLK_SPI2>;
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+				#address-cells = <1>;
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+				#size-cells = <0>;
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 				status = "disabled";
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 			};
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 			i2s0: i2s@20094000 {
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 				compatible = "nxp,lpc3220-i2s";
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 				reg = <0x20094000 0x1000>;
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+				status = "disabled";
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 			};
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 			sd: sd@20098000 {
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@@ -232,7 +237,8 @@
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 			i2s1: i2s@2009c000 {
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 				compatible = "nxp,lpc3220-i2s";
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-				reg = <0x2009C000 0x1000>;
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+				reg = <0x2009c000 0x1000>;
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+				status = "disabled";
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 			};
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 			/* UART5 first since it is the default console, ttyS0 */
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@@ -275,7 +281,7 @@
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 			i2c1: i2c@400a0000 {
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 				compatible = "nxp,pnx-i2c";
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-				reg = <0x400A0000 0x100>;
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+				reg = <0x400a0000 0x100>;
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 				interrupt-parent = <&sic1>;
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 				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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 				#address-cells = <1>;
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@@ -286,7 +292,7 @@
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 			i2c2: i2c@400a8000 {
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 				compatible = "nxp,pnx-i2c";
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-				reg = <0x400A8000 0x100>;
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+				reg = <0x400a8000 0x100>;
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 				interrupt-parent = <&sic1>;
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 				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
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 				#address-cells = <1>;
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@@ -297,7 +303,7 @@
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 			mpwm: mpwm@400e8000 {
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 				compatible = "nxp,lpc3220-motor-pwm";
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-				reg = <0x400E8000 0x78>;
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+				reg = <0x400e8000 0x78>;
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 				status = "disabled";
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 				#pwm-cells = <2>;
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 			};
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@@ -393,7 +399,7 @@
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 			timer4: timer@4002c000 {
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 				compatible = "nxp,lpc3220-timer";
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-				reg = <0x4002C000 0x1000>;
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+				reg = <0x4002c000 0x1000>;
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 				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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 				clocks = <&clk LPC32XX_CLK_TIMER4>;
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 				clock-names = "timerclk";
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@@ -411,7 +417,7 @@
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 			watchdog: watchdog@4003c000 {
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 				compatible = "nxp,pnx4008-wdt";
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-				reg = <0x4003C000 0x1000>;
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+				reg = <0x4003c000 0x1000>;
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 				clocks = <&clk LPC32XX_CLK_WDOG>;
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 			};
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@@ -450,7 +456,7 @@
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 			timer1: timer@4004c000 {
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 				compatible = "nxp,lpc3220-timer";
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-				reg = <0x4004C000 0x1000>;
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+				reg = <0x4004c000 0x1000>;
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 				interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
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 				clocks = <&clk LPC32XX_CLK_TIMER1>;
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 				clock-names = "timerclk";
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@@ -476,7 +482,7 @@
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 			pwm1: pwm@4005c000 {
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 				compatible = "nxp,lpc3220-pwm";
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-				reg = <0x4005C000 0x4>;
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+				reg = <0x4005c000 0x4>;
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 				clocks = <&clk LPC32XX_CLK_PWM1>;
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 				assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
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 				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
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@@ -485,7 +491,7 @@
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 			pwm2: pwm@4005c004 {
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 				compatible = "nxp,lpc3220-pwm";
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-				reg = <0x4005C004 0x4>;
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+				reg = <0x4005c004 0x4>;
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 				clocks = <&clk LPC32XX_CLK_PWM2>;
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 				assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
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 				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;