.. | .. |
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95 | 95 | ranges = <0x0 0x0 0x0 0xc0000000>; |
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96 | 96 | dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; |
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97 | 97 | |
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98 | | - msm_ram: msmram@c000000 { |
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| 98 | + msm_ram: sram@c000000 { |
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99 | 99 | compatible = "mmio-sram"; |
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100 | 100 | reg = <0x0c000000 0x100000>; |
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101 | 101 | ranges = <0x0 0x0c000000 0x100000>; |
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102 | 102 | #address-cells = <1>; |
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103 | 103 | #size-cells = <1>; |
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104 | 104 | |
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105 | | - sram-bm@f7000 { |
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| 105 | + bm-sram@f7000 { |
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106 | 106 | reg = <0x000f7000 0x8000>; |
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107 | 107 | }; |
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108 | 108 | }; |
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.. | .. |
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324 | 324 | clock-names = "gpio"; |
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325 | 325 | }; |
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326 | 326 | |
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| 327 | + dss: dss@02540000 { |
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| 328 | + compatible = "ti,k2g-dss"; |
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| 329 | + reg = <0x02540000 0x400>, |
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| 330 | + <0x02550000 0x1000>, |
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| 331 | + <0x02557000 0x1000>, |
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| 332 | + <0x0255a800 0x100>, |
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| 333 | + <0x0255ac00 0x100>; |
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| 334 | + reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; |
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| 335 | + clocks = <&k2g_clks 0x2 0>, |
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| 336 | + <&k2g_clks 0x2 1>; |
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| 337 | + clock-names = "fck", "vp1"; |
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| 338 | + interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; |
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| 339 | + |
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| 340 | + power-domains = <&k2g_pds 0x2>; |
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| 341 | + status = "disabled"; |
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| 342 | + #address-cells = <1>; |
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| 343 | + #size-cells = <1>; |
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| 344 | + ranges; |
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| 345 | + |
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| 346 | + max-memory-bandwidth = <230000000>; |
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| 347 | + }; |
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| 348 | + |
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327 | 349 | edma0: edma@2700000 { |
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328 | 350 | compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; |
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329 | 351 | reg = <0x02700000 0x8000>; |
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