add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/imx6sx-softing-vining-2000.dts
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@@ -1,9 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 /dts-v1/;
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@@ -96,7 +93,7 @@
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 &ecspi4 {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&pinctrl_ecspi4>;
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-	cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
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+	cs-gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
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 	status = "okay";
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 };
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@@ -355,6 +352,12 @@
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 		>;
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 	};
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+	pinctrl_pcie: pciegrp {
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+		fsl,pins = <
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+			MX6SX_PAD_NAND_DATA02__GPIO4_IO_6	0x10b0
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+		>;
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+	};
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+
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 	pinctrl_pwm1: pwm1grp-1 {
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 		fsl,pins = <
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 			/* blue LED */
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@@ -387,15 +390,15 @@
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 	pinctrl_uart1: uart1grp {
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 		fsl,pins = <
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-			MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
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-			MX6SX_PAD_GPIO1_IO05__UART1_RX		0x1b0b1
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+			MX6SX_PAD_GPIO1_IO04__UART1_DCE_TX	0x1b0b1
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+			MX6SX_PAD_GPIO1_IO05__UART1_DCE_RX	0x1b0b1
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 		>;
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 	};
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 	pinctrl_uart2: uart2grp {
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 		fsl,pins = <
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-			MX6SX_PAD_GPIO1_IO06__UART2_TX		0x1b0b1
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-			MX6SX_PAD_GPIO1_IO07__UART2_RX		0x1b0b1
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+			MX6SX_PAD_GPIO1_IO06__UART2_DCE_TX	0x1b0b1
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+			MX6SX_PAD_GPIO1_IO07__UART2_DCE_RX	0x1b0b1
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 		>;
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 	};
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@@ -493,19 +496,30 @@
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 	};
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 };
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+&pcie {
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+	pinctrl-names = "default";
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+	pinctrl-0 = <&pinctrl_pcie>;
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+	reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
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+	reset-gpio-active-high;
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+	status = "okay";
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+};
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+
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 &pwm1 {
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+	#pwm-cells = <2>;
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&pinctrl_pwm1>;
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 	status = "okay";
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 };
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 &pwm2 {
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+	#pwm-cells = <2>;
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&pinctrl_pwm2>;
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 	status = "okay";
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 };
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 &pwm6 {
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+	#pwm-cells = <2>;
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&pinctrl_pwm6>;
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 	status = "okay";