.. | .. |
---|
53 | 53 | &fec { |
---|
54 | 54 | pinctrl-names = "default"; |
---|
55 | 55 | pinctrl-0 = <&pinctrl_microsom_enet_ar8035>; |
---|
56 | | - phy-mode = "rgmii"; |
---|
57 | | - phy-reset-duration = <2>; |
---|
| 56 | + phy-mode = "rgmii-id"; |
---|
| 57 | + |
---|
| 58 | + /* |
---|
| 59 | + * The PHY seems to require a long-enough reset duration to avoid |
---|
| 60 | + * some rare issues where the PHY gets stuck in an inconsistent and |
---|
| 61 | + * non-functional state at boot-up. 10ms proved to be fine . |
---|
| 62 | + */ |
---|
| 63 | + phy-reset-duration = <10>; |
---|
58 | 64 | phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; |
---|
59 | 65 | status = "okay"; |
---|
| 66 | + |
---|
| 67 | + mdio { |
---|
| 68 | + #address-cells = <1>; |
---|
| 69 | + #size-cells = <0>; |
---|
| 70 | + |
---|
| 71 | + /* |
---|
| 72 | + * The PHY can appear at either address 0 or 4 due to the |
---|
| 73 | + * configuration (LED) pin not being pulled sufficiently. |
---|
| 74 | + */ |
---|
| 75 | + ethernet-phy@0 { |
---|
| 76 | + reg = <0>; |
---|
| 77 | + qca,clk-out-frequency = <125000000>; |
---|
| 78 | + }; |
---|
| 79 | + |
---|
| 80 | + ethernet-phy@4 { |
---|
| 81 | + reg = <4>; |
---|
| 82 | + qca,clk-out-frequency = <125000000>; |
---|
| 83 | + }; |
---|
| 84 | + }; |
---|
60 | 85 | }; |
---|
61 | 86 | |
---|
62 | 87 | &iomuxc { |
---|