add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
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@@ -1,12 +1,6 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
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- *
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- * The code contained herein is licensed under the GNU General Public
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- * License. You may obtain a copy of the GNU General Public License
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- * Version 2 or later at the following locations:
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- *
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- * http://www.opensource.org/licenses/gpl-license.html
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- * http://www.gnu.org/copyleft/gpl.html
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  */
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 #include <dt-bindings/gpio/gpio.h>
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@@ -16,6 +10,7 @@
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 	compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
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 	memory@10000000 {
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+		device_type = "memory";
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 		reg = <0x10000000 0x80000000>;
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 	};
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@@ -76,9 +71,9 @@
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&pinctrl_ecspi3>;
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 	status = "okay";
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-	cs-gpios = <&gpio4 24 0>;
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+	cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
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-	flash@0 {
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+	som_flash: flash@0 {
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 		compatible = "m25p80", "jedec,spi-nor";
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 		spi-max-frequency = <20000000>;
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 		reg = <0>;
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@@ -88,11 +83,24 @@
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 &fec {
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 	pinctrl-names = "default";
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 	pinctrl-0 = <&pinctrl_enet>;
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+	phy-handle = <&ethphy>;
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 	phy-mode = "rgmii";
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 	phy-reset-duration = <10>; /* in msecs */
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 	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
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 	phy-supply = <&vdd_eth_io_reg>;
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 	status = "disabled";
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+
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+	fec_mdio: mdio {
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+		#address-cells = <1>;
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+		#size-cells = <0>;
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+
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+		ethphy: ethernet-phy@0 {
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+			compatible = "ethernet-phy-ieee802.3-c22";
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+			reg = <0>;
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+			txc-skew-ps = <1680>;
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+			rxc-skew-ps = <1860>;
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+		};
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+	};
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 };
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 &gpmi {
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@@ -107,7 +115,7 @@
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 	pinctrl-0 = <&pinctrl_i2c1>;
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 	status = "okay";
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-	eeprom@50 {
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+	som_eeprom: eeprom@50 {
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 		compatible = "atmel,24c32";
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 		reg = <0x50>;
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 	};
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@@ -117,6 +125,7 @@
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 		reg = <0x58>;
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 		interrupt-parent = <&gpio2>;
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 		interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
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+		interrupt-controller;
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 		regulators {
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 			vddcore_reg: bcore1 {