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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/exynos5250.dtsi
....@@ -1,16 +1,16 @@
11 // SPDX-License-Identifier: GPL-2.0
22 /*
3
- * SAMSUNG EXYNOS5250 SoC device tree source
3
+ * Samsung Exynos5250 SoC device tree source
44  *
55  * Copyright (c) 2012 Samsung Electronics Co., Ltd.
66  *		http://www.samsung.com
77  *
8
- * SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
9
- * EXYNOS5250 based board files can include this file and provide
8
+ * Samsung Exynos5250 SoC device nodes are listed in this file.
9
+ * Exynos5250 based board files can include this file and provide
1010  * values for board specfic bindings.
1111  *
1212  * Note: This file does not include device nodes for all the controllers in
13
- * EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
13
+ * Exynos5250 SoC. As device tree coverage for Exynos5250 increases,
1414  * additional nodes can be added to this file.
1515  */
1616 
....@@ -59,7 +59,7 @@
5959 			operating-points-v2 = <&cpu0_opp_table>;
6060 			#cooling-cells = <2>; /* min followed by max */
6161 		};
62
-		cpu@1 {
62
+		cpu1: cpu@1 {
6363 			device_type = "cpu";
6464 			compatible = "arm,cortex-a15";
6565 			reg = <1>;
....@@ -157,20 +157,26 @@
157157 		};
158158 	};
159159 
160
+	pmu {
161
+		compatible = "arm,cortex-a15-pmu";
162
+		interrupt-parent = <&combiner>;
163
+		interrupts = <1 2>, <22 4>;
164
+	};
165
+
160166 	soc: soc {
161
-		sysram@2020000 {
167
+		sram@2020000 {
162168 			compatible = "mmio-sram";
163169 			reg = <0x02020000 0x30000>;
164170 			#address-cells = <1>;
165171 			#size-cells = <1>;
166172 			ranges = <0 0x02020000 0x30000>;
167173 
168
-			smp-sysram@0 {
174
+			smp-sram@0 {
169175 				compatible = "samsung,exynos4210-sysram";
170176 				reg = <0x0 0x1000>;
171177 			};
172178 
173
-			smp-sysram@2f000 {
179
+			smp-sram@2f000 {
174180 				compatible = "samsung,exynos4210-sysram-ns";
175181 				reg = <0x2f000 0x1000>;
176182 			};
....@@ -227,48 +233,17 @@
227233 			power-domains = <&pd_mau>;
228234 		};
229235 
230
-		timer {
231
-			compatible = "arm,armv7-timer";
232
-			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
233
-				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
234
-				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
235
-				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
236
-			/*
237
-			 * Unfortunately we need this since some versions
238
-			 * of U-Boot on Exynos don't set the CNTFRQ register,
239
-			 * so we need the value from DT.
240
-			 */
241
-			clock-frequency = <24000000>;
242
-		};
243
-
244
-		mct@101c0000 {
236
+		timer@101c0000 {
245237 			compatible = "samsung,exynos4210-mct";
246238 			reg = <0x101C0000 0x800>;
247
-			interrupt-controller;
248
-			#interrupt-cells = <2>;
249
-			interrupt-parent = <&mct_map>;
250
-			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
251
-				     <4 0>, <5 0>;
252239 			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
253240 			clock-names = "fin_pll", "mct";
254
-
255
-			mct_map: mct-map {
256
-				#interrupt-cells = <2>;
257
-				#address-cells = <0>;
258
-				#size-cells = <0>;
259
-				interrupt-map = <0x0 0 &combiner 23 3>,
260
-						<0x1 0 &combiner 23 4>,
261
-						<0x2 0 &combiner 25 2>,
262
-						<0x3 0 &combiner 25 3>,
263
-						<0x4 0 &gic 0 120 IRQ_TYPE_LEVEL_HIGH>,
264
-						<0x5 0 &gic 0 121 IRQ_TYPE_LEVEL_HIGH>;
265
-			};
266
-		};
267
-
268
-		pmu {
269
-			compatible = "arm,cortex-a15-pmu";
270
-			interrupt-parent = <&combiner>;
271
-			interrupts = <1 2>, <22 4>;
241
+			interrupts-extended = <&combiner 23 3>,
242
+					      <&combiner 23 4>,
243
+					      <&combiner 25 2>,
244
+					      <&combiner 25 3>,
245
+					      <&gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
246
+					      <&gic GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
272247 		};
273248 
274249 		pinctrl_0: pinctrl@11400000 {
....@@ -342,6 +317,53 @@
342317 			iommus = <&sysmmu_rotator>;
343318 		};
344319 
320
+		mali: gpu@11800000 {
321
+			compatible = "samsung,exynos5250-mali", "arm,mali-t604";
322
+			reg = <0x11800000 0x5000>;
323
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
324
+				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
325
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
326
+			interrupt-names = "job", "mmu", "gpu";
327
+			clocks = <&clock CLK_G3D>;
328
+			clock-names = "core";
329
+			operating-points-v2 = <&gpu_opp_table>;
330
+			power-domains = <&pd_g3d>;
331
+			status = "disabled";
332
+
333
+			gpu_opp_table: opp-table {
334
+				compatible = "operating-points-v2";
335
+
336
+				opp-100000000 {
337
+					opp-hz = /bits/ 64 <100000000>;
338
+					opp-microvolt = <925000>;
339
+				};
340
+				opp-160000000 {
341
+					opp-hz = /bits/ 64 <160000000>;
342
+					opp-microvolt = <925000>;
343
+				};
344
+				opp-266000000 {
345
+					opp-hz = /bits/ 64 <266000000>;
346
+					opp-microvolt = <1025000>;
347
+				};
348
+				opp-350000000 {
349
+					opp-hz = /bits/ 64 <350000000>;
350
+					opp-microvolt = <1075000>;
351
+				};
352
+				opp-400000000 {
353
+					opp-hz = /bits/ 64 <400000000>;
354
+					opp-microvolt = <1125000>;
355
+				};
356
+				opp-450000000 {
357
+					opp-hz = /bits/ 64 <450000000>;
358
+					opp-microvolt = <1150000>;
359
+				};
360
+				opp-533000000 {
361
+					opp-hz = /bits/ 64 <533000000>;
362
+					opp-microvolt = <1250000>;
363
+				};
364
+			};
365
+		};
366
+
345367 		tmu: tmu@10060000 {
346368 			compatible = "samsung,exynos5250-tmu";
347369 			reg = <0x10060000 0x100>;
....@@ -360,6 +382,7 @@
360382 			clock-names = "sata", "sclk_sata";
361383 			phys = <&sata_phy>;
362384 			phy-names = "sata-phy";
385
+			ports-implemented = <0x1>;
363386 			status = "disabled";
364387 		};
365388 
....@@ -450,6 +473,12 @@
450473 			clocks = <&clock CLK_SATA_PHYI2C>;
451474 			clock-names = "i2c";
452475 			status = "disabled";
476
+
477
+			sata_phy_i2c: sata-phy-i2c@38 {
478
+				compatible = "samsung,exynos-sataphy-i2c";
479
+				reg = <0x38>;
480
+				status = "disabled";
481
+			};
453482 		};
454483 
455484 		spi_0: spi@12d20000 {
....@@ -552,9 +581,9 @@
552581 			compatible = "samsung,s5pv210-i2s";
553582 			status = "disabled";
554583 			reg = <0x03830000 0x100>;
555
-			dmas = <&pdma0 10
556
-				&pdma0 9
557
-				&pdma0 8>;
584
+			dmas = <&pdma0 10>,
585
+				<&pdma0 9>,
586
+				<&pdma0 8>;
558587 			dma-names = "tx", "rx", "tx-sec";
559588 			clocks = <&clock_audss EXYNOS_I2S_BUS>,
560589 				<&clock_audss EXYNOS_I2S_BUS>,
....@@ -572,8 +601,8 @@
572601 			compatible = "samsung,s3c6410-i2s";
573602 			status = "disabled";
574603 			reg = <0x12D60000 0x100>;
575
-			dmas = <&pdma1 12
576
-				&pdma1 11>;
604
+			dmas = <&pdma1 12>,
605
+				<&pdma1 11>;
577606 			dma-names = "tx", "rx";
578607 			clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
579608 			clock-names = "iis", "i2s_opclk0";
....@@ -587,8 +616,8 @@
587616 			compatible = "samsung,s3c6410-i2s";
588617 			status = "disabled";
589618 			reg = <0x12D70000 0x100>;
590
-			dmas = <&pdma0 12
591
-				&pdma0 11>;
619
+			dmas = <&pdma0 12>,
620
+				<&pdma0 11>;
592621 			dma-names = "tx", "rx";
593622 			clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
594623 			clock-names = "iis", "i2s_opclk0";
....@@ -631,12 +660,8 @@
631660 
632661 			clocks = <&clock CLK_USB2>;
633662 			clock-names = "usbhost";
634
-			#address-cells = <1>;
635
-			#size-cells = <0>;
636
-			port@0 {
637
-				reg = <0>;
638
-				phys = <&usb2_phy_gen 1>;
639
-			};
663
+			phys = <&usb2_phy_gen 1>;
664
+			phy-names = "host";
640665 		};
641666 
642667 		ohci: usb@12120000 {
....@@ -646,12 +671,8 @@
646671 
647672 			clocks = <&clock CLK_USB2>;
648673 			clock-names = "usbhost";
649
-			#address-cells = <1>;
650
-			#size-cells = <0>;
651
-			port@0 {
652
-				reg = <0>;
653
-				phys = <&usb2_phy_gen 1>;
654
-			};
674
+			phys = <&usb2_phy_gen 1>;
675
+			phy-names = "host";
655676 		};
656677 
657678 		usb2_phy_gen: phy@12130000 {
....@@ -664,59 +685,51 @@
664685 			samsung,pmureg-phandle = <&pmu_system_controller>;
665686 		};
666687 
667
-		amba {
668
-			#address-cells = <1>;
669
-			#size-cells = <1>;
670
-			compatible = "simple-bus";
671
-			interrupt-parent = <&gic>;
672
-			ranges;
673
-
674
-			pdma0: pdma@121a0000 {
675
-				compatible = "arm,pl330", "arm,primecell";
676
-				reg = <0x121A0000 0x1000>;
677
-				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
678
-				clocks = <&clock CLK_PDMA0>;
679
-				clock-names = "apb_pclk";
680
-				#dma-cells = <1>;
681
-				#dma-channels = <8>;
682
-				#dma-requests = <32>;
683
-			};
684
-
685
-			pdma1: pdma@121b0000 {
686
-				compatible = "arm,pl330", "arm,primecell";
687
-				reg = <0x121B0000 0x1000>;
688
-				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
689
-				clocks = <&clock CLK_PDMA1>;
690
-				clock-names = "apb_pclk";
691
-				#dma-cells = <1>;
692
-				#dma-channels = <8>;
693
-				#dma-requests = <32>;
694
-			};
695
-
696
-			mdma0: mdma@10800000 {
697
-				compatible = "arm,pl330", "arm,primecell";
698
-				reg = <0x10800000 0x1000>;
699
-				interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
700
-				clocks = <&clock CLK_MDMA0>;
701
-				clock-names = "apb_pclk";
702
-				#dma-cells = <1>;
703
-				#dma-channels = <8>;
704
-				#dma-requests = <1>;
705
-			};
706
-
707
-			mdma1: mdma@11c10000 {
708
-				compatible = "arm,pl330", "arm,primecell";
709
-				reg = <0x11C10000 0x1000>;
710
-				interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
711
-				clocks = <&clock CLK_MDMA1>;
712
-				clock-names = "apb_pclk";
713
-				#dma-cells = <1>;
714
-				#dma-channels = <8>;
715
-				#dma-requests = <1>;
716
-			};
688
+		pdma0: pdma@121a0000 {
689
+			compatible = "arm,pl330", "arm,primecell";
690
+			reg = <0x121A0000 0x1000>;
691
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
692
+			clocks = <&clock CLK_PDMA0>;
693
+			clock-names = "apb_pclk";
694
+			#dma-cells = <1>;
695
+			#dma-channels = <8>;
696
+			#dma-requests = <32>;
717697 		};
718698 
719
-		gsc_0:  gsc@13e00000 {
699
+		pdma1: pdma@121b0000 {
700
+			compatible = "arm,pl330", "arm,primecell";
701
+			reg = <0x121B0000 0x1000>;
702
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
703
+			clocks = <&clock CLK_PDMA1>;
704
+			clock-names = "apb_pclk";
705
+			#dma-cells = <1>;
706
+			#dma-channels = <8>;
707
+			#dma-requests = <32>;
708
+		};
709
+
710
+		mdma0: mdma@10800000 {
711
+			compatible = "arm,pl330", "arm,primecell";
712
+			reg = <0x10800000 0x1000>;
713
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
714
+			clocks = <&clock CLK_MDMA0>;
715
+			clock-names = "apb_pclk";
716
+			#dma-cells = <1>;
717
+			#dma-channels = <8>;
718
+			#dma-requests = <1>;
719
+		};
720
+
721
+		mdma1: mdma@11c10000 {
722
+			compatible = "arm,pl330", "arm,primecell";
723
+			reg = <0x11C10000 0x1000>;
724
+			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
725
+			clocks = <&clock CLK_MDMA1>;
726
+			clock-names = "apb_pclk";
727
+			#dma-cells = <1>;
728
+			#dma-channels = <8>;
729
+			#dma-requests = <1>;
730
+		};
731
+
732
+		gsc_0: gsc@13e00000 {
720733 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
721734 			reg = <0x13e00000 0x1000>;
722735 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
....@@ -726,7 +739,7 @@
726739 			iommus = <&sysmmu_gsc0>;
727740 		};
728741 
729
-		gsc_1:  gsc@13e10000 {
742
+		gsc_1: gsc@13e10000 {
730743 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
731744 			reg = <0x13e10000 0x1000>;
732745 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
....@@ -736,7 +749,7 @@
736749 			iommus = <&sysmmu_gsc1>;
737750 		};
738751 
739
-		gsc_2:  gsc@13e20000 {
752
+		gsc_2: gsc@13e20000 {
740753 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
741754 			reg = <0x13e20000 0x1000>;
742755 			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
....@@ -746,7 +759,7 @@
746759 			iommus = <&sysmmu_gsc2>;
747760 		};
748761 
749
-		gsc_3:  gsc@13e30000 {
762
+		gsc_3: gsc@13e30000 {
750763 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
751764 			reg = <0x13e30000 0x1000>;
752765 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
....@@ -801,6 +814,27 @@
801814 			compatible = "samsung,exynos5250-dp-video-phy";
802815 			samsung,pmu-syscon = <&pmu_system_controller>;
803816 			#phy-cells = <0>;
817
+		};
818
+
819
+		mipi_phy: video-phy@10040710 {
820
+			compatible = "samsung,s5pv210-mipi-video-phy";
821
+			reg = <0x10040710 0x100>;
822
+			#phy-cells = <1>;
823
+			syscon = <&pmu_system_controller>;
824
+		};
825
+
826
+		dsi_0: dsi@14500000 {
827
+			compatible = "samsung,exynos4210-mipi-dsi";
828
+			reg = <0x14500000 0x10000>;
829
+			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
830
+			samsung,power-domain = <&pd_disp1>;
831
+			phys = <&mipi_phy 3>;
832
+			phy-names = "dsim";
833
+			clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI1>;
834
+			clock-names = "bus_clk", "sclk_mipi";
835
+			status = "disabled";
836
+			#address-cells = <1>;
837
+			#size-cells = <0>;
804838 		};
805839 
806840 		adc: adc@12d10000 {
....@@ -1057,22 +1091,35 @@
10571091 		};
10581092 	};
10591093 
1060
-	thermal-zones {
1061
-		cpu_thermal: cpu-thermal {
1062
-			polling-delay-passive = <0>;
1063
-			polling-delay = <0>;
1064
-			thermal-sensors = <&tmu 0>;
1094
+	timer {
1095
+		compatible = "arm,armv7-timer";
1096
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1097
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1098
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1099
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1100
+		/*
1101
+		 * Unfortunately we need this since some versions
1102
+		 * of U-Boot on Exynos don't set the CNTFRQ register,
1103
+		 * so we need the value from DT.
1104
+		 */
1105
+		clock-frequency = <24000000>;
1106
+	};
1107
+};
10651108 
1066
-			cooling-maps {
1067
-				map0 {
1068
-				     /* Corresponds to 800MHz at freq_table */
1069
-				     cooling-device = <&cpu0 9 9>;
1070
-				};
1071
-				map1 {
1072
-				     /* Corresponds to 200MHz at freq_table */
1073
-				     cooling-device = <&cpu0 15 15>;
1074
-			       };
1075
-		       };
1109
+&cpu_thermal {
1110
+	polling-delay-passive = <0>;
1111
+	polling-delay = <0>;
1112
+	thermal-sensors = <&tmu 0>;
1113
+
1114
+	cooling-maps {
1115
+		map0 {
1116
+			/* Corresponds to 800MHz at freq_table */
1117
+			cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
1118
+		};
1119
+		map1 {
1120
+			/* Corresponds to 200MHz at freq_table */
1121
+			cooling-device = <&cpu0 15 15>,
1122
+					 <&cpu1 15 15>;
10761123 		};
10771124 	};
10781125 };