add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/exynos4412.dtsi
..
..
@@ -45,7 +45,7 @@
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 			#cooling-cells = <2>; /* min followed by max */
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 		};
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47
 
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-		cpu@a01 {
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+		cpu1: cpu@a01 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			reg = <0xA01>;
..
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@@ -55,7 +55,7 @@
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 			#cooling-cells = <2>; /* min followed by max */
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 		};
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57
 
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-		cpu@a02 {
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+		cpu2: cpu@a02 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			reg = <0xA02>;
..
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@@ -65,7 +65,7 @@
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 			#cooling-cells = <2>; /* min followed by max */
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 		};
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67
 
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-		cpu@a03 {
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+		cpu3: cpu@a03 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			reg = <0xA03>;
..
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@@ -76,7 +76,7 @@
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 		};
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 	};
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78
 
79
-	cpu0_opp_table: opp_table0 {
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+	cpu0_opp_table: opp-table0 {
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 		compatible = "operating-points-v2";
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 		opp-shared;
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82
 
..
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@@ -188,36 +188,38 @@
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 			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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 		};
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190
 
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-		sysram@2020000 {
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+		sram@2020000 {
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 			compatible = "mmio-sram";
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 			reg = <0x02020000 0x40000>;
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 			#address-cells = <1>;
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 			#size-cells = <1>;
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 			ranges = <0 0x02020000 0x40000>;
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197
 
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-			smp-sysram@0 {
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+			smp-sram@0 {
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 				compatible = "samsung,exynos4210-sysram";
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 				reg = <0x0 0x1000>;
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 			};
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202
 
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-			smp-sysram@2f000 {
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+			smp-sram@2f000 {
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 				compatible = "samsung,exynos4210-sysram-ns";
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 				reg = <0x2f000 0x1000>;
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 			};
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 		};
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208
 
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-		pd_isp: isp-power-domain@10023ca0 {
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+		pd_isp: power-domain@10023ca0 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023CA0 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "ISP";
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 		};
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215
 
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-		l2c: l2-cache-controller@10502000 {
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+		l2c: cache-controller@10502000 {
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 			compatible = "arm,pl310-cache";
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 			reg = <0x10502000 0x1000>;
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 			cache-unified;
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 			cache-level = <2>;
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+			prefetch-data = <1>;
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+			prefetch-instr = <1>;
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 			arm,tag-latency = <2 2 1>;
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 			arm,data-latency = <3 2 1>;
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 			arm,double-linefill = <1>;
..
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@@ -243,25 +245,16 @@
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 			clock-names = "aclk200", "aclk400_mcuisp";
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 		};
245
247
 
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-		mct@10050000 {
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+		timer@10050000 {
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 			compatible = "samsung,exynos4412-mct";
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 			reg = <0x10050000 0x800>;
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-			interrupt-parent = <&mct_map>;
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-			interrupts = <0>, <1>, <2>, <3>, <4>;
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 			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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 			clock-names = "fin_pll", "mct";
253
-
254
-			mct_map: mct-map {
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-				#interrupt-cells = <1>;
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-				#address-cells = <0>;
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-				#size-cells = <0>;
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-				interrupt-map =
259
-					<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
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-					<1 &combiner 12 5>,
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-					<2 &combiner 12 6>,
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-					<3 &combiner 12 7>,
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-					<4 &gic 1 12 IRQ_TYPE_LEVEL_HIGH>;
264
-			};
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+			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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+					      <&combiner 12 5>,
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+					      <&combiner 12 6>,
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+					      <&combiner 12 7>,
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+					      <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
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 		};
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259
 
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260
 		watchdog: watchdog@10060000 {
..
..
@@ -274,7 +267,7 @@
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 		};
275
268
 
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 		adc: adc@126c0000 {
277
-			compatible = "samsung,exynos-adc-v1";
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+			compatible = "samsung,exynos4212-adc";
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 			reg = <0x126C0000 0x100>;
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 			interrupt-parent = <&combiner>;
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 			interrupts = <10 3>;
..
..
@@ -409,7 +402,7 @@
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 			status = "disabled";
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 		};
411
404
 
412
-		bus_dmc_opp_table: opp_table1 {
405
+		bus_dmc_opp_table: opp-table1 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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408
 
..
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@@ -432,10 +425,11 @@
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 			opp-400000000 {
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426
 				opp-hz = /bits/ 64 <400000000>;
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 				opp-microvolt = <1050000>;
428
+				opp-suspend;
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 			};
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 		};
437
431
 
438
-		bus_acp_opp_table: opp_table2 {
432
+		bus_acp_opp_table: opp-table2 {
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433
 			compatible = "operating-points-v2";
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 			opp-shared;
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435
 
..
..
@@ -501,7 +495,7 @@
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 			status = "disabled";
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 		};
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497
 
504
-		bus_leftbus_opp_table: opp_table3 {
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+		bus_leftbus_opp_table: opp-table3 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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501
 
..
..
@@ -520,10 +514,11 @@
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 			opp-200000000 {
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 				opp-hz = /bits/ 64 <200000000>;
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 				opp-microvolt = <1000000>;
517
+				opp-suspend;
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 			};
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519
 		};
525
520
 
526
-		bus_display_opp_table: opp_table4 {
521
+		bus_display_opp_table: opp-table4 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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524
 
..
..
@@ -535,7 +530,7 @@
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 			};
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531
 		};
537
532
 
538
-		bus_fsys_opp_table: opp_table5 {
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+		bus_fsys_opp_table: opp-table5 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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536
 
..
..
@@ -547,7 +542,7 @@
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 			};
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 		};
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544
 
550
-		bus_peri_opp_table: opp_table6 {
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+		bus_peri_opp_table: opp-table6 {
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 			compatible = "operating-points-v2";
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 			opp-shared;
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548
 
..
..
@@ -714,6 +709,53 @@
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 	cpu-offset = <0x4000>;
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 };
716
711
 
712
+&gpu {
713
+	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
714
+		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
715
+		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
720
+		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
722
+		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
723
+		     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
724
+	interrupt-names = "gp",
725
+			  "gpmmu",
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+			  "pp0",
727
+			  "ppmmu0",
728
+			  "pp1",
729
+			  "ppmmu1",
730
+			  "pp2",
731
+			  "ppmmu2",
732
+			  "pp3",
733
+			  "ppmmu3",
734
+			  "pmu";
735
+	operating-points-v2 = <&gpu_opp_table>;
736
+
737
+	gpu_opp_table: opp-table {
738
+		compatible = "operating-points-v2";
739
+
740
+		opp-160000000 {
741
+			opp-hz = /bits/ 64 <160000000>;
742
+			opp-microvolt = <875000>;
743
+		};
744
+		opp-267000000 {
745
+			opp-hz = /bits/ 64 <267000000>;
746
+			opp-microvolt = <900000>;
747
+		};
748
+		opp-350000000 {
749
+			opp-hz = /bits/ 64 <350000000>;
750
+			opp-microvolt = <950000>;
751
+		};
752
+		opp-440000000 {
753
+			opp-hz = /bits/ 64 <440000000>;
754
+			opp-microvolt = <1025000>;
755
+		};
756
+	};
757
+};
758
+
717
759
 &hdmi {
718
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 	compatible = "samsung,exynos4212-hdmi";
719
761
 };
..
..
@@ -735,6 +777,8 @@
735
777
 
736
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 &pmu {
737
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 	interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
780
+	interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
781
+	status = "okay";
738
782
 };
739
783
 
740
784
 &pmu_system_controller {