add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/exynos4210.dtsi
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@@ -8,7 +8,7 @@
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  *		www.linaro.org
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  *
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  * Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
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- * based board files can include this file and provide values for board specfic
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+ * based board files can include this file and provide values for board specific
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  * bindings.
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  *
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  * Note: This file does not include device nodes for all the controllers in
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@@ -51,7 +51,7 @@
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 			#cooling-cells = <2>; /* min followed by max */
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 		};
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-		cpu@901 {
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+		cpu1: cpu@901 {
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 			device_type = "cpu";
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 			compatible = "arm,cortex-a9";
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 			reg = <0x901>;
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@@ -72,60 +72,53 @@
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 	};
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 	soc: soc {
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-		sysram: sysram@2020000 {
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+		sysram: sram@2020000 {
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 			compatible = "mmio-sram";
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 			reg = <0x02020000 0x20000>;
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 			#address-cells = <1>;
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 			#size-cells = <1>;
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 			ranges = <0 0x02020000 0x20000>;
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-			smp-sysram@0 {
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+			smp-sram@0 {
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 				compatible = "samsung,exynos4210-sysram";
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 				reg = <0x0 0x1000>;
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 			};
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-			smp-sysram@1f000 {
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+			smp-sram@1f000 {
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 				compatible = "samsung,exynos4210-sysram-ns";
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 				reg = <0x1f000 0x1000>;
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 			};
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 		};
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-		pd_lcd1: lcd1-power-domain@10023ca0 {
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+		pd_lcd1: power-domain@10023ca0 {
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 			compatible = "samsung,exynos4210-pd";
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 			reg = <0x10023CA0 0x20>;
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 			#power-domain-cells = <0>;
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 			label = "LCD1";
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 		};
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-		l2c: l2-cache-controller@10502000 {
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+		l2c: cache-controller@10502000 {
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 			compatible = "arm,pl310-cache";
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 			reg = <0x10502000 0x1000>;
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 			cache-unified;
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 			cache-level = <2>;
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+			prefetch-data = <1>;
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+			prefetch-instr = <1>;
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 			arm,tag-latency = <2 2 1>;
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 			arm,data-latency = <2 2 1>;
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 		};
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-		mct: mct@10050000 {
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+		mct: timer@10050000 {
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 			compatible = "samsung,exynos4210-mct";
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 			reg = <0x10050000 0x800>;
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-			interrupt-parent = <&mct_map>;
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-			interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
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 			clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
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 			clock-names = "fin_pll", "mct";
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-
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-			mct_map: mct-map {
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-				#interrupt-cells = <1>;
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-				#address-cells = <0>;
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-				#size-cells = <0>;
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-				interrupt-map =
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-					<0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
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-					<1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
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-					<2 &combiner 12 6>,
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-					<3 &combiner 12 7>,
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-					<4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
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-					<5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
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-			};
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+			interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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+					      <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
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+					      <&combiner 12 6>,
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+					      <&combiner 12 7>,
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+					      <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
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+					      <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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 		};
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123
 
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 		watchdog: watchdog@10060000 {
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@@ -298,6 +291,7 @@
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 			opp-400000000 {
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 				opp-hz = /bits/ 64 <400000000>;
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 				opp-microvolt = <1150000>;
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+				opp-suspend;
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 			};
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 		};
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..
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@@ -367,29 +361,28 @@
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 			};
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 			opp-200000000 {
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 				opp-hz = /bits/ 64 <200000000>;
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+				opp-suspend;
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 			};
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 		};
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 	};
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+};
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-	thermal-zones {
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-		cpu_thermal: cpu-thermal {
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-			polling-delay-passive = <0>;
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-			polling-delay = <0>;
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-			thermal-sensors = <&tmu 0>;
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+&cpu_alert0 {
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+	temperature = <85000>; /* millicelsius */
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+};
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-			trips {
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-				cpu_alert0: cpu-alert-0 {
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-				temperature = <85000>; /* millicelsius */
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-				};
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-				cpu_alert1: cpu-alert-1 {
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-				temperature = <100000>; /* millicelsius */
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-				};
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-				cpu_alert2: cpu-alert-2 {
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-				temperature = <110000>; /* millicelsius */
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-				};
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-			};
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-		};
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-	};
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+&cpu_alert1 {
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+	temperature = <100000>; /* millicelsius */
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+};
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+
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+&cpu_alert2 {
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+	temperature = <110000>; /* millicelsius */
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+};
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+
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+&cpu_thermal {
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+	polling-delay-passive = <0>;
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+	polling-delay = <0>;
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+	thermal-sensors = <&tmu 0>;
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 };
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 &gic {
..
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@@ -447,6 +440,43 @@
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 	samsung,lcd-wb;
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 };
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+&gpu {
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+	interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
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+		     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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+	interrupt-names = "gp",
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+			  "gpmmu",
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+			  "pp0",
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+			  "ppmmu0",
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+			  "pp1",
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+			  "ppmmu1",
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+			  "pp2",
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+			  "ppmmu2",
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+			  "pp3",
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+			  "ppmmu3";
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+	operating-points-v2 = <&gpu_opp_table>;
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+
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+	gpu_opp_table: opp_table {
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+		compatible = "operating-points-v2";
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+
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+		opp-160000000 {
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+			opp-hz = /bits/ 64 <160000000>;
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+			opp-microvolt = <950000>;
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+		};
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+		opp-267000000 {
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+			opp-hz = /bits/ 64 <267000000>;
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+			opp-microvolt = <1050000>;
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+		};
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+	};
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+};
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+
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 &mdma1 {
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 	power-domains = <&pd_lcd0>;
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 };
..
..
@@ -459,6 +489,12 @@
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 		 <&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
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 };
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+&pmu {
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+	interrupts = <2 2>, <3 2>;
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+	interrupt-affinity = <&cpu0>, <&cpu1>;
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+	status = "okay";
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+};
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+
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 &pmu_system_controller {
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 	clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
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 			"clkout4", "clkout8", "clkout9";