forked from ~ljy/RK356X_SDK_RELEASE

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2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d 
 kernel/arch/arm/boot/dts/exynos3250.dtsi
....@@ -97,56 +97,52 @@
9797 		};
9898 	};
9999 
100
+	xusbxti: clock-0 {
101
+		compatible = "fixed-clock";
102
+		clock-frequency = <0>;
103
+		#clock-cells = <0>;
104
+		clock-output-names = "xusbxti";
105
+	};
106
+
107
+	xxti: clock-1 {
108
+		compatible = "fixed-clock";
109
+		clock-frequency = <0>;
110
+		#clock-cells = <0>;
111
+		clock-output-names = "xxti";
112
+	};
113
+
114
+	xtcxo: clock-2 {
115
+		compatible = "fixed-clock";
116
+		clock-frequency = <0>;
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+		#clock-cells = <0>;
118
+		clock-output-names = "xtcxo";
119
+	};
120
+
121
+	pmu {
122
+		compatible = "arm,cortex-a7-pmu";
123
+		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
124
+			     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
125
+	};
126
+
100127 	soc: soc {
101128 		compatible = "simple-bus";
102129 		#address-cells = <1>;
103130 		#size-cells = <1>;
104131 		ranges;
105132 
106
-		fixed-rate-clocks {
107
-			#address-cells = <1>;
108
-			#size-cells = <0>;
109
-
110
-			xusbxti: clock@0 {
111
-				compatible = "fixed-clock";
112
-				#address-cells = <1>;
113
-				#size-cells = <0>;
114
-				reg = <0>;
115
-				clock-frequency = <0>;
116
-				#clock-cells = <0>;
117
-				clock-output-names = "xusbxti";
118
-			};
119
-
120
-			xxti: clock@1 {
121
-				compatible = "fixed-clock";
122
-				reg = <1>;
123
-				clock-frequency = <0>;
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-				#clock-cells = <0>;
125
-				clock-output-names = "xxti";
126
-			};
127
-
128
-			xtcxo: clock@2 {
129
-				compatible = "fixed-clock";
130
-				reg = <2>;
131
-				clock-frequency = <0>;
132
-				#clock-cells = <0>;
133
-				clock-output-names = "xtcxo";
134
-			};
135
-		};
136
-
137
-		sysram@2020000 {
133
+		sram@2020000 {
138134 			compatible = "mmio-sram";
139135 			reg = <0x02020000 0x40000>;
140136 			#address-cells = <1>;
141137 			#size-cells = <1>;
142138 			ranges = <0 0x02020000 0x40000>;
143139 
144
-			smp-sysram@0 {
140
+			smp-sram@0 {
145141 				compatible = "samsung,exynos4210-sysram";
146142 				reg = <0x0 0x1000>;
147143 			};
148144 
149
-			smp-sysram@3f000 {
145
+			smp-sram@3f000 {
150146 				compatible = "samsung,exynos4210-sysram-ns";
151147 				reg = <0x3f000 0x1000>;
152148 			};
....@@ -261,7 +257,7 @@
261257 					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
262258 		};
263259 
264
-		mct@10050000 {
260
+		timer@10050000 {
265261 			compatible = "samsung,exynos4210-mct";
266262 			reg = <0x10050000 0x800>;
267263 			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
....@@ -310,8 +306,7 @@
310306 		sysmmu_jpeg: sysmmu@11a60000 {
311307 			compatible = "samsung,exynos-sysmmu";
312308 			reg = <0x11a60000 0x1000>;
313
-			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
314
-				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
309
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
315310 			clock-names = "sysmmu", "master";
316311 			clocks = <&cmu CLK_SMMUJPEG>, <&cmu CLK_JPEG>;
317312 			power-domains = <&pd_cam>;
....@@ -351,8 +346,7 @@
351346 		sysmmu_fimd0: sysmmu@11e20000 {
352347 			compatible = "samsung,exynos-sysmmu";
353348 			reg = <0x11e20000 0x1000>;
354
-			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
355
-				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
349
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
356350 			clock-names = "sysmmu", "master";
357351 			clocks = <&cmu CLK_SMMUFIMD0>, <&cmu CLK_FIMD0>;
358352 			power-domains = <&pd_lcd0>;
....@@ -360,7 +354,7 @@
360354 		};
361355 
362356 		hsotg: hsotg@12480000 {
363
-			compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
357
+			compatible = "samsung,s3c6400-hsotg";
364358 			reg = <0x12480000 0x20000>;
365359 			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
366360 			clocks = <&cmu CLK_USBOTG>;
....@@ -416,38 +410,30 @@
416410 			status = "disabled";
417411 		};
418412 
419
-		amba {
420
-			compatible = "simple-bus";
421
-			#address-cells = <1>;
422
-			#size-cells = <1>;
423
-			ranges;
413
+		pdma0: pdma@12680000 {
414
+			compatible = "arm,pl330", "arm,primecell";
415
+			reg = <0x12680000 0x1000>;
416
+			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
417
+			clocks = <&cmu CLK_PDMA0>;
418
+			clock-names = "apb_pclk";
419
+			#dma-cells = <1>;
420
+			#dma-channels = <8>;
421
+			#dma-requests = <32>;
422
+		};
424423 
425
-			pdma0: pdma@12680000 {
426
-				compatible = "arm,pl330", "arm,primecell";
427
-				reg = <0x12680000 0x1000>;
428
-				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
429
-				clocks = <&cmu CLK_PDMA0>;
430
-				clock-names = "apb_pclk";
431
-				#dma-cells = <1>;
432
-				#dma-channels = <8>;
433
-				#dma-requests = <32>;
434
-			};
435
-
436
-			pdma1: pdma@12690000 {
437
-				compatible = "arm,pl330", "arm,primecell";
438
-				reg = <0x12690000 0x1000>;
439
-				interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
440
-				clocks = <&cmu CLK_PDMA1>;
441
-				clock-names = "apb_pclk";
442
-				#dma-cells = <1>;
443
-				#dma-channels = <8>;
444
-				#dma-requests = <32>;
445
-			};
424
+		pdma1: pdma@12690000 {
425
+			compatible = "arm,pl330", "arm,primecell";
426
+			reg = <0x12690000 0x1000>;
427
+			interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
428
+			clocks = <&cmu CLK_PDMA1>;
429
+			clock-names = "apb_pclk";
430
+			#dma-cells = <1>;
431
+			#dma-channels = <8>;
432
+			#dma-requests = <32>;
446433 		};
447434 
448435 		adc: adc@126c0000 {
449
-			compatible = "samsung,exynos3250-adc",
450
-				     "samsung,exynos-adc-v2";
436
+			compatible = "samsung,exynos3250-adc";
451437 			reg = <0x126C0000 0x100>;
452438 			interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
453439 			clock-names = "adc", "sclk";
....@@ -456,6 +442,39 @@
456442 			io-channel-ranges;
457443 			samsung,syscon-phandle = <&pmu_system_controller>;
458444 			status = "disabled";
445
+		};
446
+
447
+		gpu: gpu@13000000 {
448
+			compatible = "samsung,exynos4210-mali", "arm,mali-400";
449
+			reg = <0x13000000 0x10000>;
450
+			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
451
+				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
452
+				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
453
+				     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
454
+				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
455
+				     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
456
+				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
457
+				     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
458
+				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
459
+				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
460
+				     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
461
+			interrupt-names = "gp",
462
+					  "gpmmu",
463
+					  "pp0",
464
+					  "ppmmu0",
465
+					  "pp1",
466
+					  "ppmmu1",
467
+					  "pp2",
468
+					  "ppmmu2",
469
+					  "pp3",
470
+					  "ppmmu3",
471
+					  "pmu";
472
+			clocks = <&cmu CLK_G3D>,
473
+				 <&cmu CLK_SCLK_G3D>;
474
+			clock-names = "bus", "core";
475
+			power-domains = <&pd_g3d>;
476
+			status = "disabled";
477
+			/* TODO: operating points for DVFS, assigned clock as 134 MHz */
459478 		};
460479 
461480 		mfc: codec@13400000 {
....@@ -471,8 +490,7 @@
471490 		sysmmu_mfc: sysmmu@13620000 {
472491 			compatible = "samsung,exynos-sysmmu";
473492 			reg = <0x13620000 0x1000>;
474
-			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
475
-				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
493
+			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
476494 			clock-names = "sysmmu", "master";
477495 			clocks = <&cmu CLK_SMMUMFC_L>, <&cmu CLK_MFC>;
478496 			power-domains = <&pd_mfc>;
....@@ -671,12 +689,6 @@
671689 				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
672690 			#pwm-cells = <3>;
673691 			status = "disabled";
674
-		};
675
-
676
-		pmu {
677
-			compatible = "arm,cortex-a7-pmu";
678
-			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
679
-				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
680692 		};
681693 
682694 		ppmu_dmc0: ppmu_dmc0@106a0000 {