.. | .. |
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122 | 122 | ranges = <0 0xf7000000 0x1000000>; |
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123 | 123 | interrupt-parent = <&gic>; |
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124 | 124 | |
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125 | | - sdhci0: sdhci@ab0000 { |
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| 125 | + sdhci0: mmc@ab0000 { |
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126 | 126 | compatible = "mrvl,pxav3-mmc"; |
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127 | 127 | reg = <0xab0000 0x200>; |
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128 | 128 | clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; |
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.. | .. |
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131 | 131 | status = "disabled"; |
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132 | 132 | }; |
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133 | 133 | |
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134 | | - sdhci1: sdhci@ab0800 { |
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| 134 | + sdhci1: mmc@ab0800 { |
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135 | 135 | compatible = "mrvl,pxav3-mmc"; |
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136 | 136 | reg = <0xab0800 0x200>; |
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137 | 137 | clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO>; |
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.. | .. |
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140 | 140 | status = "disabled"; |
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141 | 141 | }; |
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142 | 142 | |
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143 | | - sdhci2: sdhci@ab1000 { |
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| 143 | + sdhci2: mmc@ab1000 { |
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144 | 144 | compatible = "mrvl,pxav3-mmc"; |
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145 | 145 | reg = <0xab1000 0x200>; |
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146 | 146 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
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.. | .. |
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149 | 149 | status = "disabled"; |
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150 | 150 | }; |
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151 | 151 | |
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152 | | - l2: l2-cache-controller@ac0000 { |
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| 152 | + l2: cache-controller@ac0000 { |
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153 | 153 | compatible = "arm,pl310-cache"; |
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154 | 154 | reg = <0xac0000 0x1000>; |
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155 | 155 | cache-unified; |
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