hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/arm/boot/dts/berlin2.dtsi
....@@ -77,7 +77,7 @@
7777
7878 ranges = <0 0xf7000000 0x1000000>;
7979
80
- sdhci0: sdhci@ab0000 {
80
+ sdhci0: mmc@ab0000 {
8181 compatible = "mrvl,pxav3-mmc";
8282 reg = <0xab0000 0x200>;
8383 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
....@@ -86,7 +86,7 @@
8686 status = "disabled";
8787 };
8888
89
- sdhci1: sdhci@ab0800 {
89
+ sdhci1: mmc@ab0800 {
9090 compatible = "mrvl,pxav3-mmc";
9191 reg = <0xab0800 0x200>;
9292 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
....@@ -95,7 +95,7 @@
9595 status = "disabled";
9696 };
9797
98
- sdhci2: sdhci@ab1000 {
98
+ sdhci2: mmc@ab1000 {
9999 compatible = "mrvl,pxav3-mmc";
100100 reg = <0xab1000 0x200>;
101101 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
....@@ -106,7 +106,7 @@
106106 status = "disabled";
107107 };
108108
109
- l2: l2-cache-controller@ac0000 {
109
+ l2: cache-controller@ac0000 {
110110 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
111111 reg = <0xac0000 0x1000>;
112112 cache-unified;