.. | .. |
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77 | 77 | |
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78 | 78 | ranges = <0 0xf7000000 0x1000000>; |
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79 | 79 | |
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80 | | - sdhci0: sdhci@ab0000 { |
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| 80 | + sdhci0: mmc@ab0000 { |
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81 | 81 | compatible = "mrvl,pxav3-mmc"; |
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82 | 82 | reg = <0xab0000 0x200>; |
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83 | 83 | clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>; |
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.. | .. |
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86 | 86 | status = "disabled"; |
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87 | 87 | }; |
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88 | 88 | |
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89 | | - sdhci1: sdhci@ab0800 { |
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| 89 | + sdhci1: mmc@ab0800 { |
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90 | 90 | compatible = "mrvl,pxav3-mmc"; |
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91 | 91 | reg = <0xab0800 0x200>; |
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92 | 92 | clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>; |
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.. | .. |
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95 | 95 | status = "disabled"; |
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96 | 96 | }; |
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97 | 97 | |
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98 | | - sdhci2: sdhci@ab1000 { |
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| 98 | + sdhci2: mmc@ab1000 { |
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99 | 99 | compatible = "mrvl,pxav3-mmc"; |
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100 | 100 | reg = <0xab1000 0x200>; |
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101 | 101 | interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
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.. | .. |
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106 | 106 | status = "disabled"; |
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107 | 107 | }; |
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108 | 108 | |
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109 | | - l2: l2-cache-controller@ac0000 { |
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| 109 | + l2: cache-controller@ac0000 { |
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110 | 110 | compatible = "marvell,tauros3-cache", "arm,pl310-cache"; |
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111 | 111 | reg = <0xac0000 0x1000>; |
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112 | 112 | cache-unified; |
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