hc
2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d
kernel/arch/arm/boot/dts/bcm21664.dtsi
....@@ -16,9 +16,9 @@
1616
1717 #include "dt-bindings/clock/bcm21664.h"
1818
19
-#include "skeleton.dtsi"
20
-
2119 / {
20
+ #address-cells = <1>;
21
+ #size-cells = <1>;
2222 model = "BCM21664 SoC";
2323 compatible = "brcm,bcm21664";
2424 interrupt-parent = <&gic>;
....@@ -90,7 +90,7 @@
9090 reg-io-width = <4>;
9191 };
9292
93
- L2: l2-cache {
93
+ L2: cache-controller@3ff20000 {
9494 compatible = "arm,pl310-cache";
9595 reg = <0x3ff20000 0x1000>;
9696 cache-unified;
....@@ -295,21 +295,21 @@
295295 clock-frequency = <156000000>;
296296 };
297297
298
- root_ccu: root_ccu {
298
+ root_ccu: root_ccu@35001000 {
299299 compatible = BCM21664_DT_ROOT_CCU_COMPAT;
300300 reg = <0x35001000 0x0f00>;
301301 #clock-cells = <1>;
302302 clock-output-names = "frac_1m";
303303 };
304304
305
- aon_ccu: aon_ccu {
305
+ aon_ccu: aon_ccu@35002000 {
306306 compatible = BCM21664_DT_AON_CCU_COMPAT;
307307 reg = <0x35002000 0x0f00>;
308308 #clock-cells = <1>;
309309 clock-output-names = "hub_timer";
310310 };
311311
312
- master_ccu: master_ccu {
312
+ master_ccu: master_ccu@3f001000 {
313313 compatible = BCM21664_DT_MASTER_CCU_COMPAT;
314314 reg = <0x3f001000 0x0f00>;
315315 #clock-cells = <1>;
....@@ -323,7 +323,7 @@
323323 "sdio4_sleep";
324324 };
325325
326
- slave_ccu: slave_ccu {
326
+ slave_ccu: slave_ccu@3e011000 {
327327 compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
328328 reg = <0x3e011000 0x0f00>;
329329 #clock-cells = <1>;