.. | .. |
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16 | 16 | |
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17 | 17 | #include "dt-bindings/clock/bcm21664.h" |
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18 | 18 | |
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19 | | -#include "skeleton.dtsi" |
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20 | | - |
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21 | 19 | / { |
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| 20 | + #address-cells = <1>; |
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| 21 | + #size-cells = <1>; |
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22 | 22 | model = "BCM21664 SoC"; |
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23 | 23 | compatible = "brcm,bcm21664"; |
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24 | 24 | interrupt-parent = <&gic>; |
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.. | .. |
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90 | 90 | reg-io-width = <4>; |
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91 | 91 | }; |
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92 | 92 | |
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93 | | - L2: l2-cache { |
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| 93 | + L2: cache-controller@3ff20000 { |
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94 | 94 | compatible = "arm,pl310-cache"; |
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95 | 95 | reg = <0x3ff20000 0x1000>; |
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96 | 96 | cache-unified; |
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.. | .. |
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295 | 295 | clock-frequency = <156000000>; |
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296 | 296 | }; |
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297 | 297 | |
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298 | | - root_ccu: root_ccu { |
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| 298 | + root_ccu: root_ccu@35001000 { |
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299 | 299 | compatible = BCM21664_DT_ROOT_CCU_COMPAT; |
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300 | 300 | reg = <0x35001000 0x0f00>; |
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301 | 301 | #clock-cells = <1>; |
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302 | 302 | clock-output-names = "frac_1m"; |
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303 | 303 | }; |
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304 | 304 | |
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305 | | - aon_ccu: aon_ccu { |
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| 305 | + aon_ccu: aon_ccu@35002000 { |
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306 | 306 | compatible = BCM21664_DT_AON_CCU_COMPAT; |
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307 | 307 | reg = <0x35002000 0x0f00>; |
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308 | 308 | #clock-cells = <1>; |
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309 | 309 | clock-output-names = "hub_timer"; |
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310 | 310 | }; |
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311 | 311 | |
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312 | | - master_ccu: master_ccu { |
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| 312 | + master_ccu: master_ccu@3f001000 { |
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313 | 313 | compatible = BCM21664_DT_MASTER_CCU_COMPAT; |
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314 | 314 | reg = <0x3f001000 0x0f00>; |
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315 | 315 | #clock-cells = <1>; |
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.. | .. |
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323 | 323 | "sdio4_sleep"; |
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324 | 324 | }; |
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325 | 325 | |
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326 | | - slave_ccu: slave_ccu { |
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| 326 | + slave_ccu: slave_ccu@3e011000 { |
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327 | 327 | compatible = BCM21664_DT_SLAVE_CCU_COMPAT; |
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328 | 328 | reg = <0x3e011000 0x0f00>; |
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329 | 329 | #clock-cells = <1>; |
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