.. | .. |
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34 | 34 | #include <dt-bindings/interrupt-controller/irq.h> |
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35 | 35 | #include <dt-bindings/clock/bcm-cygnus.h> |
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36 | 36 | |
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37 | | -#include "skeleton.dtsi" |
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38 | | - |
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39 | 37 | / { |
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| 38 | + #address-cells = <1>; |
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| 39 | + #size-cells = <1>; |
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40 | 40 | compatible = "brcm,cygnus"; |
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41 | 41 | model = "Broadcom Cygnus SoC"; |
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42 | 42 | interrupt-parent = <&gic>; |
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43 | 43 | |
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44 | 44 | aliases { |
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45 | 45 | ethernet0 = ð0; |
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| 46 | + }; |
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| 47 | + |
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| 48 | + memory@0 { |
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| 49 | + device_type = "memory"; |
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| 50 | + reg = <0 0>; |
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46 | 51 | }; |
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47 | 52 | |
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48 | 53 | cpus { |
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.. | .. |
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64 | 69 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
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65 | 70 | }; |
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66 | 71 | |
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67 | | - core { |
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| 72 | + core@19000000 { |
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68 | 73 | compatible = "simple-bus"; |
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69 | 74 | ranges = <0x00000000 0x19000000 0x1000000>; |
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70 | 75 | #address-cells = <1>; |
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.. | .. |
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86 | 91 | <0x20100 0x100>; |
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87 | 92 | }; |
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88 | 93 | |
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89 | | - L2: l2-cache { |
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| 94 | + L2: cache-controller@22000 { |
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90 | 95 | compatible = "arm,pl310-cache"; |
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91 | 96 | reg = <0x22000 0x1000>; |
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92 | 97 | cache-unified; |
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.. | .. |
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229 | 234 | compatible = "arm,sp805" , "arm,primecell"; |
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230 | 235 | reg = <0x18009000 0x1000>; |
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231 | 236 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
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232 | | - clocks = <&axi81_clk>; |
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233 | | - clock-names = "apb_pclk"; |
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| 237 | + clocks = <&axi81_clk>, <&axi81_clk>; |
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| 238 | + clock-names = "wdog_clk", "apb_pclk"; |
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234 | 239 | }; |
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235 | 240 | |
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236 | 241 | gpio_ccm: gpio@1800a000 { |
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