.. | .. |
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23 | 23 | /dts-v1/; |
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24 | 24 | #include <dt-bindings/interrupt-controller/irq.h> |
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25 | 25 | #include <dt-bindings/gpio/gpio.h> |
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26 | | -#include "skeleton.dtsi" |
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27 | 26 | |
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28 | 27 | / { |
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| 28 | + #address-cells = <1>; |
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| 29 | + #size-cells = <1>; |
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29 | 30 | model = "ARM RealView PB11MPcore"; |
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30 | 31 | compatible = "arm,realview-pb11mp"; |
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31 | 32 | |
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.. | .. |
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39 | 40 | }; |
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40 | 41 | |
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41 | 42 | memory { |
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| 43 | + device_type = "memory"; |
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42 | 44 | /* |
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43 | 45 | * The PB11MPCore has 512 MiB memory @ 0x70000000 |
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44 | 46 | * and the first 256 are also remapped @ 0x00000000 |
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.. | .. |
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90 | 92 | <0x1f000100 0x100>; |
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91 | 93 | }; |
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92 | 94 | |
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93 | | - L2: l2-cache { |
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| 95 | + L2: cache-controller { |
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94 | 96 | compatible = "arm,l220-cache"; |
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95 | 97 | reg = <0x1f002000 0x1000>; |
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96 | 98 | interrupt-parent = <&intc_tc11mp>; |
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.. | .. |
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233 | 235 | compatible = "arm,versatile-flash", "cfi-flash"; |
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234 | 236 | reg = <0x40000000 0x04000000>; |
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235 | 237 | bank-width = <4>; |
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| 238 | + partitions { |
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| 239 | + compatible = "arm,arm-firmware-suite"; |
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| 240 | + }; |
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236 | 241 | }; |
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237 | 242 | |
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238 | 243 | flash1@44000000 { |
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.. | .. |
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240 | 245 | compatible = "arm,versatile-flash", "cfi-flash"; |
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241 | 246 | reg = <0x44000000 0x04000000>; |
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242 | 247 | bank-width = <4>; |
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| 248 | + partitions { |
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| 249 | + compatible = "arm,arm-firmware-suite"; |
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| 250 | + }; |
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243 | 251 | }; |
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244 | 252 | |
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245 | 253 | bridge { |
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.. | .. |
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538 | 546 | interrupt-parent = <&intc_pb11mp>; |
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539 | 547 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; |
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540 | 548 | clocks = <&wdogclk>, <&pclk>; |
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541 | | - clock-names = "wdogclk", "apb_pclk"; |
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| 549 | + clock-names = "wdog_clk", "apb_pclk"; |
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542 | 550 | status = "disabled"; |
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543 | 551 | }; |
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544 | 552 | |
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.. | .. |
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548 | 556 | interrupt-parent = <&intc_pb11mp>; |
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549 | 557 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>; |
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550 | 558 | clocks = <&wdogclk>, <&pclk>; |
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551 | | - clock-names = "wdogclk", "apb_pclk"; |
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| 559 | + clock-names = "wdog_clk", "apb_pclk"; |
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552 | 560 | }; |
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553 | 561 | |
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554 | 562 | timer01: timer@10011000 { |
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.. | .. |
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560 | 568 | clocks = <&sp810_syscon 0>, |
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561 | 569 | <&sp810_syscon 1>, |
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562 | 570 | <&pclk>; |
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563 | | - clock-names = "timerclk0", |
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564 | | - "timerclk1", |
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| 571 | + clock-names = "timer0clk", |
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| 572 | + "timer1clk", |
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565 | 573 | "apb_pclk"; |
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566 | 574 | }; |
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567 | 575 | |
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.. | .. |
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574 | 582 | clocks = <&sp810_syscon 2>, |
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575 | 583 | <&sp810_syscon 3>, |
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576 | 584 | <&pclk>; |
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577 | | - clock-names = "timerclk2", |
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578 | | - "timerclk3", |
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| 585 | + clock-names = "timer0clk", |
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| 586 | + "timer1clk", |
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579 | 587 | "apb_pclk"; |
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580 | 588 | }; |
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581 | 589 | |
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.. | .. |
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637 | 645 | timer45: timer@10018000 { |
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638 | 646 | compatible = "arm,sp804", "arm,primecell"; |
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639 | 647 | reg = <0x10018000 0x1000>; |
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640 | | - clocks = <&timclk>, <&pclk>; |
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641 | | - clock-names = "timer", "apb_pclk"; |
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| 648 | + clocks = <&timclk>, <&timclk>, <&pclk>; |
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| 649 | + clock-names = "timer0clk", "timer1clk", "apb_pclk"; |
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642 | 650 | status = "disabled"; |
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643 | 651 | }; |
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644 | 652 | |
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645 | 653 | timer67: timer@10019000 { |
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646 | 654 | compatible = "arm,sp804", "arm,primecell"; |
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647 | 655 | reg = <0x10019000 0x1000>; |
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648 | | - clocks = <&timclk>, <&pclk>; |
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649 | | - clock-names = "timer", "apb_pclk"; |
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| 656 | + clocks = <&timclk>, <&timclk>, <&pclk>; |
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| 657 | + clock-names = "timer0clk", "timer1clk", "apb_pclk"; |
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650 | 658 | status = "disabled"; |
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651 | 659 | }; |
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652 | 660 | |
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