add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
..
..
@@ -1,15 +1,13 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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- * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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+ * Copyright (C) 2014-2016 Texas Instruments Incorporated - https://www.ti.com/
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  */
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 /dts-v1/;
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-#include "dra74x.dtsi"
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+#include "am5728.dtsi"
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 #include "am57xx-commercial-grade.dtsi"
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 #include "dra74x-mmc-iodelay.dtsi"
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+#include "dra74-ipu-dsp-common.dtsi"
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 #include <dt-bindings/gpio/gpio.h>
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 #include <dt-bindings/interrupt-controller/irq.h>
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..
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@@ -51,6 +49,40 @@
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 		vin-supply = <&main_12v0>;
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 		regulator-always-on;
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 		regulator-boot-on;
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+	};
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+
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+	reserved-memory {
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+		#address-cells = <2>;
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+		#size-cells = <2>;
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+		ranges;
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+
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+		ipu2_memory_region: ipu2-memory@95800000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x95800000 0x0 0x3800000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		dsp1_memory_region: dsp1-memory@99000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x99000000 0x0 0x4000000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		ipu1_memory_region: ipu1-memory@9d000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x9d000000 0x0 0x2000000>;
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+			reusable;
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+			status = "okay";
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+		};
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+
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+		dsp2_memory_region: dsp2-memory@9f000000 {
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+			compatible = "shared-dma-pool";
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+			reg = <0x0 0x9f000000 0x0 0x800000>;
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+			reusable;
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+			status = "okay";
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+		};
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 	};
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 	vdd_3v3: fixedregulator-vdd_3v3 {
..
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@@ -403,7 +435,7 @@
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 	};
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 };
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-&gpio7 {
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+&gpio7_target {
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 	ti,no-reset-on-init;
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 	ti,no-idle-on-init;
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 };
..
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@@ -419,7 +451,7 @@
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 			      <&dra7_pmx_core 0x3f8>;
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 };
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-&davinci_mdio {
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+&davinci_mdio_sw {
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 	phy0: ethernet-phy@1 {
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 		reg = <1>;
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 	};
..
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@@ -429,21 +461,20 @@
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 	};
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 };
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-&mac {
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+&mac_sw {
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 	status = "okay";
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-	dual_emac;
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 };
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-&cpsw_emac0 {
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+&cpsw_port1 {
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 	phy-handle = <&phy0>;
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-	phy-mode = "rgmii";
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-	dual_emac_res_vlan = <1>;
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+	phy-mode = "rgmii-rxid";
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+	ti,dual-emac-pvid = <1>;
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 };
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-&cpsw_emac1 {
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+&cpsw_port2 {
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 	phy-handle = <&phy1>;
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-	phy-mode = "rgmii";
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-	dual_emac_res_vlan = <2>;
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+	phy-mode = "rgmii-rxid";
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+	ti,dual-emac-pvid = <2>;
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 };
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 &mmc1 {
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@@ -550,13 +581,13 @@
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 };
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 &dss {
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-	status = "ok";
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+	status = "okay";
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 	vdda_video-supply = <&ldoln_reg>;
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 };
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 &hdmi {
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-	status = "ok";
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+	status = "okay";
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 	vdda-supply = <&ldo4_reg>;
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592
 
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 	port {
..
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@@ -567,13 +598,13 @@
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 };
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 &pcie1_rc {
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-	status = "ok";
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+	status = "okay";
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 	gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
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 };
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 &mcasp3 {
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 	#sound-dai-cells = <0>;
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-	assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
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+	assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
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 	assigned-clock-parents = <&sys_clkin2>;
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 	status = "okay";
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..
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@@ -587,22 +618,22 @@
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 	rx-num-evt = <32>;
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 };
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-&mailbox5 {
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+&ipu2 {
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 	status = "okay";
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-	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
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-		status = "okay";
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-	};
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-	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
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-		status = "okay";
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-	};
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+	memory-region = <&ipu2_memory_region>;
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 };
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-&mailbox6 {
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+&ipu1 {
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 	status = "okay";
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-	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
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-		status = "okay";
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-	};
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-	mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
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-		status = "okay";
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-	};
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+	memory-region = <&ipu1_memory_region>;
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+};
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+
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+&dsp1 {
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+	status = "okay";
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+	memory-region = <&dsp1_memory_region>;
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+};
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+
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+&dsp2 {
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+	status = "okay";
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+	memory-region = <&dsp2_memory_region>;
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 };