add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/am43xx-clocks.dtsi
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@@ -1,11 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Device Tree Source for AM43xx clock data
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  *
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  * Copyright (C) 2013 Texas Instruments, Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 &scm_clocks {
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 	sys_clkin_ck: sys_clkin_ck@40 {
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@@ -764,73 +761,123 @@
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 };
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 &prcm {
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-	l4_wkup_cm: l4_wkup_cm@2800 {
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+	wkup_cm: wkup-cm@2800 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x2800 0x400>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x2800 0x400>;
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-		l4_wkup_clkctrl: clk@20 {
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+		l3s_tsc_clkctrl: l3s-tsc-clkctrl@120 {
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 			compatible = "ti,clkctrl";
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-			reg = <0x20 0x34c>;
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+			reg = <0x120 0x4>;
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 			#clock-cells = <2>;
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 		};
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+
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+		l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@228 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x228 0xc>;
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+			#clock-cells = <2>;
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+		};
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+
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+		l4_wkup_clkctrl: l4-wkup-clkctrl@220 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x220 0x4>, <0x328 0x44>;
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+			#clock-cells = <2>;
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+		};
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+
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 	};
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-	mpu_cm: mpu_cm@8300 {
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+	mpu_cm: mpu-cm@8300 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x8300 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x8300 0x100>;
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-		mpu_clkctrl: clk@20 {
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+		mpu_clkctrl: mpu-clkctrl@20 {
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 			compatible = "ti,clkctrl";
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 			reg = <0x20 0x4>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	gfx_l3_cm: gfx_l3_cm@8400 {
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+	gfx_l3_cm: gfx-l3-cm@8400 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x8400 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x8400 0x100>;
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-		gfx_l3_clkctrl: clk@20 {
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+		gfx_l3_clkctrl: gfx-l3-clkctrl@20 {
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 			compatible = "ti,clkctrl";
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 			reg = <0x20 0x4>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	l4_rtc_cm: l4_rtc_cm@8500 {
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+	l4_rtc_cm: l4-rtc-cm@8500 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x8500 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x8500 0x100>;
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-		l4_rtc_clkctrl: clk@20 {
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+		l4_rtc_clkctrl: l4-rtc-clkctrl@20 {
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 			compatible = "ti,clkctrl";
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 			reg = <0x20 0x4>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	l4_per_cm: l4_per_cm@8800 {
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+	per_cm: per-cm@8800 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x8800 0xc00>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x8800 0xc00>;
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-		l4_per_clkctrl: clk@20 {
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+		l3_clkctrl: l3-clkctrl@20 {
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 			compatible = "ti,clkctrl";
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-			reg = <0x20 0xb04>;
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+			reg = <0x20 0x3c>, <0x78 0x2c>;
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 			#clock-cells = <2>;
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 		};
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+
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+		l3s_clkctrl: l3s-clkctrl@68 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x68 0xc>, <0x220 0x4c>;
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+			#clock-cells = <2>;
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+		};
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+
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+		pruss_ocp_clkctrl: pruss-ocp-clkctrl@320 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x320 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		l4ls_clkctrl: l4ls-clkctrl@420 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x420 0x1a4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		emif_clkctrl: emif-clkctrl@720 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x720 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		dss_clkctrl: dss-clkctrl@a20 {
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+			compatible = "ti,clkctrl";
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+			reg = <0xa20 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@b20 {
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+			compatible = "ti,clkctrl";
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+			reg = <0xb20 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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 	};
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 };