add boot partition size

hc

2023-12-11 d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d

 kernel/arch/arm/boot/dts/am33xx-clocks.dtsi
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@@ -1,11 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Device Tree Source for AM33xx clock data
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  *
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  * Copyright (C) 2013 Texas Instruments, Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 &scm_clocks {
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 	sys_clkin_ck: sys_clkin_ck@40 {
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@@ -334,49 +331,49 @@
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 	timer1_fck: timer1_fck@528 {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
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+		clocks = <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
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 		reg = <0x0528>;
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 	};
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 	timer2_fck: timer2_fck@508 {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x0508>;
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 	};
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 	timer3_fck: timer3_fck@50c {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x050c>;
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 	};
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 	timer4_fck: timer4_fck@510 {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x0510>;
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 	};
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 	timer5_fck: timer5_fck@518 {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x0518>;
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 	};
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365
 
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 	timer6_fck: timer6_fck@51c {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x051c>;
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 	};
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 	timer7_fck: timer7_fck@504 {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x0504>;
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 	};
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..
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@@ -407,7 +404,7 @@
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 	wdt1_fck: wdt1_fck@538 {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&clk_rc32k_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x0538>;
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 	};
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@@ -477,7 +474,7 @@
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 	gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
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 		#clock-cells = <0>;
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 		compatible = "ti,mux-clock";
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-		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
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+		clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
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 		reg = <0x053c>;
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 	};
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@@ -539,86 +536,140 @@
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 };
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 &prcm {
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-	l4_per_cm: l4_per_cm@0 {
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+	per_cm: per-cm@0 {
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 		compatible = "ti,omap4-cm";
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-		reg = <0x0 0x200>;
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+		reg = <0x0 0x400>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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-		ranges = <0 0x0 0x200>;
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+		ranges = <0 0x0 0x400>;
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-		l4_per_clkctrl: clk@14 {
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+		l4ls_clkctrl: l4ls-clkctrl@38 {
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 			compatible = "ti,clkctrl";
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-			reg = <0x14 0x13c>;
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+			reg = <0x38 0x2c>, <0x6c 0x28>, <0xac 0xc>, <0xc0 0x1c>, <0xec 0xc>, <0x10c 0x8>, <0x130 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		l3s_clkctrl: l3s-clkctrl@1c {
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+			compatible = "ti,clkctrl";
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+			reg = <0x1c 0x4>, <0x30 0x8>, <0x68 0x4>, <0xf8 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		l3_clkctrl: l3-clkctrl@24 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x24 0xc>, <0x94 0x10>, <0xbc 0x4>, <0xdc 0x8>, <0xfc 0x8>;
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+			#clock-cells = <2>;
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+		};
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+
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+		l4hs_clkctrl: l4hs-clkctrl@120 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x120 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		pruss_ocp_clkctrl: pruss-ocp-clkctrl@e8 {
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+			compatible = "ti,clkctrl";
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+			reg = <0xe8 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x0 0x18>;
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+			#clock-cells = <2>;
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+		};
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+
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+		lcdc_clkctrl: lcdc-clkctrl@18 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x18 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
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+			compatible = "ti,clkctrl";
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+			reg = <0x14c 0x4>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	l4_wkup_cm: l4_wkup_cm@400 {
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+	wkup_cm: wkup-cm@400 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x400 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x400 0x100>;
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-		l4_wkup_clkctrl: clk@4 {
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+		l4_wkup_clkctrl: l4-wkup-clkctrl@0 {
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 			compatible = "ti,clkctrl";
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-			reg = <0x4 0xd4>;
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+			reg = <0x0 0x10>, <0xb4 0x24>;
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+			#clock-cells = <2>;
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+		};
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+
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+		l3_aon_clkctrl: l3-aon-clkctrl@14 {
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+			compatible = "ti,clkctrl";
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+			reg = <0x14 0x4>;
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+			#clock-cells = <2>;
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+		};
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+
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+		l4_wkup_aon_clkctrl: l4-wkup-aon-clkctrl@b0 {
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+			compatible = "ti,clkctrl";
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+			reg = <0xb0 0x4>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	mpu_cm: mpu_cm@600 {
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+	mpu_cm: mpu-cm@600 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x600 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x600 0x100>;
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-		mpu_clkctrl: clk@4 {
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+		mpu_clkctrl: mpu-clkctrl@0 {
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 			compatible = "ti,clkctrl";
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-			reg = <0x4 0x4>;
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+			reg = <0x0 0x8>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	l4_rtc_cm: l4_rtc_cm@800 {
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+	l4_rtc_cm: l4-rtc-cm@800 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x800 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x800 0x100>;
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-		l4_rtc_clkctrl: clk@0 {
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+		l4_rtc_clkctrl: l4-rtc-clkctrl@0 {
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 			compatible = "ti,clkctrl";
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 			reg = <0x0 0x4>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	gfx_l3_cm: gfx_l3_cm@900 {
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+	gfx_l3_cm: gfx-l3-cm@900 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0x900 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x900 0x100>;
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-		gfx_l3_clkctrl: clk@4 {
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+		gfx_l3_clkctrl: gfx-l3-clkctrl@0 {
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 			compatible = "ti,clkctrl";
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-			reg = <0x4 0x4>;
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+			reg = <0x0 0x8>;
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 			#clock-cells = <2>;
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 		};
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 	};
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-	l4_cefuse_cm: l4_cefuse_cm@a00 {
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+	l4_cefuse_cm: l4-cefuse-cm@a00 {
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 		compatible = "ti,omap4-cm";
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 		reg = <0xa00 0x100>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0xa00 0x100>;
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-		l4_cefuse_clkctrl: clk@20 {
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+		l4_cefuse_clkctrl: l4-cefuse-clkctrl@0 {
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 			compatible = "ti,clkctrl";
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-			reg = <0x20 0x4>;
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+			reg = <0x0 0x24>;
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 			#clock-cells = <2>;
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 		};
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 	};